Re: [staging/cadence-aarch64 PATCH v3 1/6] CadencePkg: Add libraries for Cadence CSP platform.

[Ard Biesheuvel <ard.biesheuvel@linaro.org>]

On 22 June 2017 at 14:50, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Thu, Jun 22, 2017 at 10:31:56AM +0100, Scott Telford wrote:
>> Add libraries (CadenceCspLib, CadenceCspSecLib,
>> CadenceCspResetSystemLib) to support the Cadence Configurable System
>> Platform (CSP) configured with a single ARM Cortex-A53, GIC-500,
>> Cadence UART and Cadence PCIe Root Complex.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.0
>> Signed-off-by: Scott Telford <stelford@cadence.com>
>
> I'd like for Ard to comment on the bits he raised last time, but from
> my point of view:
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
>

Looks fine to me

Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>


>> ---
>>  CadencePkg/Include/Library/CspSysReg.h             |  37 ++++++
>>  .../CadenceCspLib/AArch64/ArmPlatformHelper.S      |  55 +++++++++
>>  CadencePkg/Library/CadenceCspLib/CadenceCspLib.c   | 133 +++++++++++++++++++++
>>  CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf |  68 +++++++++++
>>  .../Library/CadenceCspLib/CadenceCspLibMem.c       | 116 ++++++++++++++++++
>>  .../Library/CadenceCspLib/CadenceCspLibSec.inf     |  52 ++++++++
>>  .../CadenceCspResetSystemLib.c                     |  82 +++++++++++++
>>  .../CadenceCspResetSystemLib.inf                   |  40 +++++++
>>  .../Library/CadenceCspSecLib/AArch64/CspBoot.S     |  49 ++++++++
>>  .../Library/CadenceCspSecLib/AArch64/GicV3.S       |  67 +++++++++++
>>  .../Library/CadenceCspSecLib/CadenceCspSecLib.inf  |  44 +++++++
>>  CadencePkg/Library/CadenceCspSecLib/CspSec.c       |  79 ++++++++++++
>>  12 files changed, 822 insertions(+)
>>  create mode 100644 CadencePkg/Include/Library/CspSysReg.h
>>  create mode 100644 CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
>>  create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.c
>>  create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
>>  create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c
>>  create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
>>  create mode 100644 CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c
>>  create mode 100644 CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
>>  create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S
>>  create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S
>>  create mode 100644 CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
>>  create mode 100644 CadencePkg/Library/CadenceCspSecLib/CspSec.c
>>
>> diff --git a/CadencePkg/Include/Library/CspSysReg.h b/CadencePkg/Include/Library/CspSysReg.h
>> new file mode 100644
>> index 0000000..4d3ac925
>> --- /dev/null
>> +++ b/CadencePkg/Include/Library/CspSysReg.h
>> @@ -0,0 +1,37 @@
>> +/** @file
>> +*  Cadence CSP system register offsets.
>> +*  Copyright (c) 2017, Cadence Design Systems. All rights reserved.
>> +*
>> +*  This program and the accompanying materials are licensed and made
>> +*  available under the terms and conditions of the BSD License which
>> +*  accompanies this distribution.  The full text of the license may be
>> +*  found at http://opensource.org/licenses/bsd-license.php
>> +*
>> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +**/
>> +
>> +#ifndef __CSP_SYS_REG_H__
>> +#define __CSP_SYS_REG_H__
>> +
>> +// Cadence CSP system register offsets
>> +#define CSP_SYSREG_VERSION          0x00
>> +#define CSP_SYSREG_CPU_FREQ         0x04
>> +#define CSP_SYSREG_STATUS           0x08
>> +#define CSP_SYSREG_RUN_STALL        0x0C
>> +#define CSP_SYSREG_SW_RESET         0x10
>> +#define CSP_SYSREG_CORE1_RESET      0x14
>> +#define CSP_SYSREG_SCRATCH_REG_0    0x18
>> +#define CSP_SYSREG_PROC_INTERRUPT   0x1C
>> +#define CSP_SYSREG_SCRATCH_REG_1    0x20
>> +#define CSP_SYSREG_SCRATCH_REG_2    0x24
>> +#define CSP_SYSREG_SCRATCH_REG_3    0x28
>> +#define CSP_SYSREG_SCRATCH_REG_4    0x2C
>> +#define CSP_SYSREG_SCRATCH_REG_5    0x30
>> +#define CSP_SYSREG_SCRATCH_REG_6    0x34
>> +#define CSP_SYSREG_SET_INTERRUPT    0x38
>> +#define CSP_SYSREG_CLR_INTERRUPT    0x3C
>> +#define CSP_SYSREG_DIP_SWITCHES     0x40
>> +
>> +#endif
>> diff --git a/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S b/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
>> new file mode 100644
>> index 0000000..8832673
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
>> @@ -0,0 +1,55 @@
>> +#
>> +#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
>> +#
>> +#  This program and the accompanying materials
>> +#  are licensed and made available under the terms and conditions of the BSD License
>> +#  which accompanies this distribution.  The full text of the license may be found at
>> +#  http://opensource.org/licenses/bsd-license.php
>> +#
>> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +#
>> +
>> +#include <AsmMacroIoLibV8.h>
>> +#include <Library/ArmLib.h>
>> +
>> +ASM_FUNC(ArmPlatformPeiBootAction)
>> +  ret
>> +
>> +//UINTN
>> +//ArmPlatformGetPrimaryCoreMpId (
>> +//  VOID
>> +//  );
>> +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
>> +  MOV32  (w0, FixedPcdGet32 (PcdArmPrimaryCore))
>> +  ret
>> +
>> +//UINTN
>> +//ArmPlatformIsPrimaryCore (
>> +//  IN UINTN MpId
>> +//  );
>> +ASM_FUNC(ArmPlatformIsPrimaryCore)
>> +  MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
>> +  and   x0, x0, x1
>> +  MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
>> +  cmp   w0, w1
>> +  b.ne  1f
>> +  mov   x0, #1
>> +  ret
>> +1:
>> +  mov   x0, #0
>> +  ret
>> +
>> +//UINTN
>> +//ArmPlatformGetCorePosition (
>> +//  IN UINTN MpId
>> +//  );
>> +// With this function: CorePos = (ClusterId * 4) + CoreId
>> +ASM_FUNC(ArmPlatformGetCorePosition)
>> +  and   x1, x0, #ARM_CORE_MASK
>> +  and   x0, x0, #ARM_CLUSTER_MASK
>> +  add   x0, x1, x0, LSR #6
>> +  ret
>> +
>> +ASM_FUNCTION_REMOVE_IF_UNREFERENCED
>> diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLib.c b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.c
>> new file mode 100644
>> index 0000000..fc200a1
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.c
>> @@ -0,0 +1,133 @@
>> +/** @file
>> +*
>> +*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
>> +*  Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +*
>> +*  This program and the accompanying materials
>> +*  are licensed and made available under the terms and conditions of the BSD License
>> +*  which accompanies this distribution.  The full text of the license may be found at
>> +*  http://opensource.org/licenses/bsd-license.php
>> +*
>> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +**/
>> +
>> +#include <Library/ArmLib.h>
>> +#include <Library/ArmPlatformLib.h>
>> +#include <Library/CspSysReg.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/PcdLib.h>
>> +
>> +#include <Ppi/ArmMpCoreInfo.h>
>> +
>> +
>> +ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] = {
>> +  {
>> +    // Cluster 0, Core 0
>> +    0x0, 0x0,
>> +
>> +    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
>> +    (EFI_PHYSICAL_ADDRESS)0,
>> +    (EFI_PHYSICAL_ADDRESS)0,
>> +    (EFI_PHYSICAL_ADDRESS)0,
>> +    (UINT64)0xFFFFFFFF
>> +  }
>> +};
>> +
>> +
>> +
>> +/**
>> +  Return the current Boot Mode
>> +
>> +  This function returns the boot reason on the platform
>> +
>> +**/
>> +EFI_BOOT_MODE
>> +ArmPlatformGetBootMode (
>> +  VOID
>> +  )
>> +{
>> +  return BOOT_WITH_FULL_CONFIGURATION;
>> +}
>> +
>> +/**
>> +  Initialize controllers that must setup in the normal world
>> +
>> +  This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
>> +  in the PEI phase.
>> +
>> +**/
>> +RETURN_STATUS
>> +ArmPlatformInitialize (
>> +  IN  UINTN                     MpId
>> +  )
>> +{
>> +  UINTN CspScratchReg2;
>> +
>> +  if (!ArmPlatformIsPrimaryCore (MpId)) {
>> +    return RETURN_SUCCESS;
>> +  }
>> +
>> +  // CSP System Register initialisation
>> +  CspScratchReg2 = PcdGet64 (PcdCspSysRegBase) + CSP_SYSREG_SCRATCH_REG_2;
>> +  MmioWrite32 ((UINTN)CspScratchReg2, 0x1);
>> +  MmioWrite32 ((UINTN)CspScratchReg2, 0x3);
>> +
>> +  return RETURN_SUCCESS;
>> +}
>> +
>> +/**
>> +  Initialize the system (or sometimes called permanent) memory
>> +
>> +  This memory is generally represented by the DRAM.
>> +
>> +**/
>> +VOID
>> +ArmPlatformInitializeSystemMemory (
>> +  VOID
>> +  )
>> +{
>> +}
>> +
>> +STATIC
>> +EFI_STATUS
>> +PrePeiCoreGetMpCoreInfo (
>> +  OUT UINTN                   *CoreCount,
>> +  OUT ARM_CORE_INFO           **ArmCoreTable
>> +  )
>> +{
>> +  if (ArmIsMpCore()) {
>> +    *CoreCount    = sizeof(mArmPlatformNullMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
>> +    *ArmCoreTable = mArmPlatformNullMpCoreInfoTable;
>> +    return EFI_SUCCESS;
>> +  } else {
>> +    return EFI_UNSUPPORTED;
>> +  }
>> +}
>> +
>> +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
>> +
>> +STATIC EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
>> +  {
>> +    EFI_PEI_PPI_DESCRIPTOR_PPI,
>> +    &gArmMpCoreInfoPpiGuid,
>> +    &mMpCoreInfoPpi
>> +  }
>> +};
>> +
>> +VOID
>> +ArmPlatformGetPlatformPpiList (
>> +  OUT UINTN                   *PpiListSize,
>> +  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
>> +  )
>> +{
>> +  if (ArmIsMpCore()) {
>> +    *PpiListSize = sizeof(gPlatformPpiTable);
>> +    *PpiList = gPlatformPpiTable;
>> +  } else {
>> +    *PpiListSize = 0;
>> +    *PpiList = NULL;
>> +  }
>> +}
>> +
>> diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
>> new file mode 100644
>> index 0000000..a09a89e
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
>> @@ -0,0 +1,68 @@
>> +#/* @file
>> +#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
>> +#  Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +#
>> +#  This program and the accompanying materials
>> +#  are licensed and made available under the terms and conditions of the BSD License
>> +#  which accompanies this distribution.  The full text of the license may be found at
>> +#  http://opensource.org/licenses/bsd-license.php
>> +#
>> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +#*/
>> +
>> +[Defines]
>> +  INF_VERSION                    = 1.25
>> +  BASE_NAME                      = CadenceCspLib
>> +  FILE_GUID                      = 13392a39-0fd2-4ec1-8541-1a7b5f0005d9
>> +  MODULE_TYPE                    = BASE
>> +  VERSION_STRING                 = 1.0
>> +  LIBRARY_CLASS                  = ArmPlatformLib
>> +
>> +[Packages]
>> +  MdePkg/MdePkg.dec
>> +  MdeModulePkg/MdeModulePkg.dec
>> +  EmbeddedPkg/EmbeddedPkg.dec
>> +  ArmPkg/ArmPkg.dec
>> +  ArmPlatformPkg/ArmPlatformPkg.dec
>> +  CadencePkg/CadenceCspPkg.dec
>> +
>> +[LibraryClasses]
>> +  ArmLib
>> +  MemoryAllocationLib
>> +  SerialPortLib
>> +  DebugLib
>> +  HobLib
>> +
>> +[Sources.common]
>> +  CadenceCspLib.c
>> +  CadenceCspLibMem.c
>> +
>> +[Sources.AArch64]
>> +  AArch64/ArmPlatformHelper.S
>> +
>> +[FixedPcd]
>> +  gArmTokenSpaceGuid.PcdSystemMemoryBase
>> +  gArmTokenSpaceGuid.PcdSystemMemorySize
>> +
>> +  gArmTokenSpaceGuid.PcdSecureFdBaseAddress
>> +  gArmTokenSpaceGuid.PcdSecureFdSize
>> +  gArmTokenSpaceGuid.PcdFdBaseAddress
>> +  gArmTokenSpaceGuid.PcdFdSize
>> +
>> +  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
>> +  gArmTokenSpaceGuid.PcdArmPrimaryCore
>> +
>> +  gArmTokenSpaceGuid.PcdGicDistributorBase
>> +  gArmTokenSpaceGuid.PcdGicRedistributorsBase
>> +
>> +  gCadenceCspTokenSpaceGuid.PcdCspSysRegBase
>> +  gCadenceCspTokenSpaceGuid.PcdCspSysRegSize
>> +
>> +  gCadenceCspTokenSpaceGuid.PcdCspSerialBase
>> +  gCadenceCspTokenSpaceGuid.PcdCspSerialSize
>> +
>> +  gCadenceCspTokenSpaceGuid.PcdPcieRootPortBaseAddress
>> +  gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress
>> +  gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceSize
>> diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c b/CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c
>> new file mode 100644
>> index 0000000..5eccb7c
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c
>> @@ -0,0 +1,116 @@
>> +/** @file
>> +*
>> +*  Copyright (c) 2011, ARM Limited. All rights reserved.
>> +*  Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +*
>> +*  This program and the accompanying materials
>> +*  are licensed and made available under the terms and conditions of the BSD License
>> +*  which accompanies this distribution.  The full text of the license may be found at
>> +*  http://opensource.org/licenses/bsd-license.php
>> +*
>> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +**/
>> +
>> +#include <Library/ArmPlatformLib.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/MemoryAllocationLib.h>
>> +#include <Library/PcdLib.h>
>> +
>> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          14
>> +
>> +#define GICD_SZ SIZE_64KB
>> +#define GICR_SZ SIZE_128KB
>> +
>> +/**
>> +  Return the Virtual Memory Map of your platform
>> +
>> +  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
>> +
>> +  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
>> +                                    Virtual Memory mapping. This array must be ended by a zero-filled
>> +                                    entry
>> +
>> +**/
>> +VOID
>> +ArmPlatformGetVirtualMemoryMap (
>> +  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
>> +  )
>> +{
>> +  UINTN                         Index = 0;
>> +  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
>> +
>> +  ASSERT(VirtualMemoryMap != NULL);
>> +
>> +  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
>> +  if (VirtualMemoryTable == NULL) {
>> +    return;
>> +  }
>> +  // SRAM
>> +  VirtualMemoryTable[Index].PhysicalBase = PcdGet64(PcdSystemMemoryBase);
>> +  VirtualMemoryTable[Index].VirtualBase  = PcdGet64(PcdSystemMemoryBase);
>> +  VirtualMemoryTable[Index].Length       = PcdGet64(PcdSystemMemorySize);
>> +  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
>> +
>> +  // CDNS UART
>> +  VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdCspSerialBase);
>> +  VirtualMemoryTable[Index].VirtualBase  = PcdGet64(PcdCspSerialBase);
>> +  VirtualMemoryTable[Index].Length       = PcdGet32(PcdCspSerialSize);
>> +  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> +
>> +  // UEFI ROM (Secure)
>> +  VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdSecureFdBaseAddress);
>> +  VirtualMemoryTable[Index].VirtualBase  = PcdGet64(PcdSecureFdBaseAddress);
>> +  VirtualMemoryTable[Index].Length       = PcdGet32(PcdSecureFdSize);
>> +  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
>> +
>> +  // UEFI ROM (Normal)
>> +  VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdFdBaseAddress);
>> +  VirtualMemoryTable[Index].VirtualBase  = PcdGet64(PcdFdBaseAddress);
>> +  VirtualMemoryTable[Index].Length       = PcdGet32(PcdFdSize);
>> +  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
>> +
>> +  // CSP SysRegs
>> +  VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdCspSysRegBase);
>> +  VirtualMemoryTable[Index].VirtualBase  = PcdGet64(PcdCspSysRegBase);
>> +  VirtualMemoryTable[Index].Length       = PcdGet32(PcdCspSysRegSize);
>> +  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> +
>> +  // GIC Distributor
>> +  VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdGicDistributorBase);
>> +  VirtualMemoryTable[Index].VirtualBase  = PcdGet64(PcdGicDistributorBase);
>> +  VirtualMemoryTable[Index].Length       = GICD_SZ;
>> +  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> +
>> +  // GIC Redistributor
>> +  VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdGicRedistributorsBase);
>> +  VirtualMemoryTable[Index].VirtualBase  = PcdGet64(PcdGicRedistributorsBase);
>> +  VirtualMemoryTable[Index].Length       = GICR_SZ;
>> +  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> +
>> +  // PCIe RP
>> +  VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdPcieRootPortBaseAddress);
>> +  VirtualMemoryTable[Index].VirtualBase  = PcdGet64(PcdPcieRootPortBaseAddress);
>> +  VirtualMemoryTable[Index].Length       = SIZE_8MB;
>> +  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> +
>> +  //
>> +  // PCI Configuration Space (AXI region)
>> +  //
>> +  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);
>> +  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);
>> +  VirtualMemoryTable[Index].Length          = PcdGet64 (PcdPciConfigurationSpaceSize);
>> +  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> +
>> +  // End of Table
>> +  VirtualMemoryTable[++Index].PhysicalBase = 0;
>> +  VirtualMemoryTable[Index].VirtualBase  = 0;
>> +  VirtualMemoryTable[Index].Length       = 0;
>> +  VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;
>> +
>> +  ASSERT(Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
>> +
>> +  *VirtualMemoryMap = VirtualMemoryTable;
>> +}
>> diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf b/CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
>> new file mode 100644
>> index 0000000..dd6c5c3
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
>> @@ -0,0 +1,52 @@
>> +#/* @file
>> +#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
>> +#  Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +#
>> +#  This program and the accompanying materials
>> +#  are licensed and made available under the terms and conditions of the BSD License
>> +#  which accompanies this distribution.  The full text of the license may be found at
>> +#  http://opensource.org/licenses/bsd-license.php
>> +#
>> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +#*/
>> +
>> +[Defines]
>> +  INF_VERSION                    = 1.25
>> +  BASE_NAME                      = CadenceCspLibSec
>> +  FILE_GUID                      = 3008d873-1400-48d8-abda-6ac9cce97246
>> +  MODULE_TYPE                    = BASE
>> +  VERSION_STRING                 = 1.0
>> +  LIBRARY_CLASS                  = ArmPlatformLib
>> +
>> +[Packages]
>> +  ArmPkg/ArmPkg.dec
>> +  ArmPlatformPkg/ArmPlatformPkg.dec
>> +  CadencePkg/CadenceCspPkg.dec
>> +  MdeModulePkg/MdeModulePkg.dec
>> +  MdePkg/MdePkg.dec
>> +
>> +[LibraryClasses]
>> +  ArmLib
>> +  DebugLib
>> +
>> +[Sources.common]
>> +  CadenceCspLib.c
>> +
>> +[Sources.AARCH64]
>> +  AArch64/ArmPlatformHelper.S
>> +
>> +[FixedPcd]
>> +  gArmTokenSpaceGuid.PcdSystemMemoryBase
>> +  gArmTokenSpaceGuid.PcdSystemMemorySize
>> +  gArmTokenSpaceGuid.PcdFvBaseAddress
>> +
>> +  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
>> +  gArmTokenSpaceGuid.PcdArmPrimaryCore
>> +
>> +  gCadenceCspTokenSpaceGuid.PcdCspSysRegBase
>> +  gCadenceCspTokenSpaceGuid.PcdCspSysRegSize
>> +
>> +[Ppis]
>> +  gArmMpCoreInfoPpiGuid
>> diff --git a/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c
>> new file mode 100644
>> index 0000000..20ea1a6
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c
>> @@ -0,0 +1,82 @@
>> +/** @file
>> +  Library to support ResetSystem Runtime call.
>> +
>> +  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
>> +  Copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
>> +  Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +
>> +  This program and the accompanying materials
>> +  are licensed and made available under the terms and conditions of the BSD License
>> +  which accompanies this distribution.  The full text of the license may be found at
>> +  http://opensource.org/licenses/bsd-license.php
>> +
>> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +
>> +**/
>> +
>> +#include <PiDxe.h>
>> +
>> +#include <Library/BaseLib.h>
>> +#include <Library/CspSysReg.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/EfiResetSystemLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/PcdLib.h>
>> +
>> +/**
>> +  Resets the entire platform.
>> +
>> +  @param  ResetType             The type of reset to perform.
>> +  @param  ResetStatus           The status code for the reset.
>> +  @param  DataSize              The size, in bytes, of WatchdogData.
>> +  @param  ResetData             For a ResetType of EfiResetCold, EfiResetWarm, or
>> +                                EfiResetShutdown the data buffer starts with a Null-terminated
>> +                                Unicode string, optionally followed by additional binary data.
>> +
>> +**/
>> +EFI_STATUS
>> +EFIAPI
>> +LibResetSystem (
>> +  IN EFI_RESET_TYPE   ResetType,
>> +  IN EFI_STATUS       ResetStatus,
>> +  IN UINTN            DataSize,
>> +  IN CHAR16           *ResetData OPTIONAL
>> +  )
>> +{
>> +  switch (ResetType) {
>> +  case EfiResetPlatformSpecific:
>> +    // Map the platform specific reset as reboot
>> +  case EfiResetWarm:
>> +    // Map a warm reset into a cold reset
>> +  case EfiResetShutdown:
>> +    // Map a shutdown into a cold reset
>> +  case EfiResetCold:
>> +    MmioWrite16((PcdGet64(PcdCspSysRegBase) + CSP_SYSREG_SW_RESET), 0xDEAD);
>> +    break;
>> +  default:
>> +    return EFI_INVALID_PARAMETER;
>> +  }
>> +
>> +  ASSERT(FALSE);
>> +  return EFI_UNSUPPORTED;
>> +}
>> +
>> +/**
>> +  Initialize any infrastructure required for LibResetSystem () to function.
>> +
>> +  @param  ImageHandle   The firmware allocated handle for the EFI image.
>> +  @param  SystemTable   A pointer to the EFI System Table.
>> +
>> +  @retval EFI_SUCCESS   The constructor always returns EFI_SUCCESS.
>> +
>> +**/
>> +EFI_STATUS
>> +EFIAPI
>> +LibInitializeResetSystem (
>> +  IN EFI_HANDLE        ImageHandle,
>> +  IN EFI_SYSTEM_TABLE  *SystemTable
>> +  )
>> +{
>> +  return EFI_SUCCESS;
>> +}
>> diff --git a/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
>> new file mode 100644
>> index 0000000..66491ee
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
>> @@ -0,0 +1,40 @@
>> +#/** @file
>> +# Library to support ResetSystem Runtime call.
>> +#
>> +# Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
>> +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +#
>> +#  This program and the accompanying materials
>> +#  are licensed and made available under the terms and conditions of the BSD License
>> +#  which accompanies this distribution. The full text of the license may be found at
>> +#  http://opensource.org/licenses/bsd-license.php
>> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +#
>> +#**/
>> +
>> +[Defines]
>> +  INF_VERSION                    = 1.25
>> +  BASE_NAME                      = CadenceCspResetSystemLib
>> +  FILE_GUID                      = 4b1bc734-7534-4baa-b33f-7f5caa743996
>> +  MODULE_TYPE                    = BASE
>> +  VERSION_STRING                 = 1.0
>> +  LIBRARY_CLASS                  = EfiResetSystemLib
>> +
>> +
>> +[Sources.common]
>> +  CadenceCspResetSystemLib.c
>> +
>> +[Packages]
>> +  CadencePkg/CadenceCspPkg.dec
>> +  EmbeddedPkg/EmbeddedPkg.dec
>> +  MdePkg/MdePkg.dec
>> +
>> +[LibraryClasses]
>> +  IoLib
>> +  DebugLib
>> +  PcdLib
>> +
>> +[FixedPcd]
>> +  gCadenceCspTokenSpaceGuid.PcdCspSysRegBase
>> diff --git a/CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S b/CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S
>> new file mode 100644
>> index 0000000..f0f411e
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S
>> @@ -0,0 +1,49 @@
>> +//
>> +//  Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
>> +//
>> +//  This program and the accompanying materials
>> +//  are licensed and made available under the terms and conditions of the BSD License
>> +//  which accompanies this distribution.  The full text of the license may be found at
>> +//  http://opensource.org/licenses/bsd-license.php
>> +//
>> +//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +//
>> +//
>> +
>> +#include <AsmMacroIoLibV8.h>
>> +#include <Base.h>
>> +#include <Library/ArmPlatformLib.h>
>> +#include <AutoGen.h>
>> +
>> +.text
>> +.align 3
>> +
>> +GCC_ASM_EXPORT(ArmPlatformSecBootAction)
>> +GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)
>> +
>> +/**
>> +  Call at the beginning of the platform boot up
>> +
>> +  This function allows the firmware platform to do extra actions at the early
>> +  stage of the platform power up.
>> +
>> +  Note: This function must be implemented in assembler as there is no stack set up yet
>> +
>> +**/
>> +ASM_PFX(ArmPlatformSecBootAction):
>> +  ret
>> +
>> +/**
>> +  Initialize the memory where the initial stacks will reside
>> +
>> +  This memory can contain the initial stacks (Secure and Secure Monitor stacks).
>> +  In some platform, this region is already initialized and the implementation of this function can
>> +  do nothing. This memory can also represent the Secure RAM.
>> +  This function is called before the satck has been set up. Its implementation must ensure the stack
>> +  pointer is not used (probably required to use assembly language)
>> +
>> +**/
>> +ASM_PFX(ArmPlatformSecBootMemoryInit):
>> +  // The SMC does not need to be initialized for RTSM
>> +  ret
>> diff --git a/CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S b/CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S
>> new file mode 100644
>> index 0000000..e136a8d
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S
>> @@ -0,0 +1,67 @@
>> +//
>> +//  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
>> +//
>> +//  This program and the accompanying materials
>> +//  are licensed and made available under the terms and conditions of the BSD License
>> +//  which accompanies this distribution.  The full text of the license may be found at
>> +//  http://opensource.org/licenses/bsd-license.php
>> +//
>> +//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +//
>> +//
>> +
>> +#include <AsmMacroIoLibV8.h>
>> +#include <Chipset/AArch64.h>
>> +
>> +#ifndef __clang__
>> +// Register definitions used by GCC for GICv3 access.
>> +// These are defined by ARMCC, so keep them in the GCC specific code for now.
>> +#define ICC_SRE_EL2     S3_4_C12_C9_5
>> +#define ICC_SRE_EL3     S3_6_C12_C12_5
>> +#define ICC_CTLR_EL1    S3_0_C12_C12_4
>> +#define ICC_CTLR_EL3    S3_6_C12_C12_4
>> +#define ICC_PMR_EL1     S3_0_C4_C6_0
>> +#endif
>> +
>> +.text
>> +.align 3
>> +
>> +GCC_ASM_EXPORT(InitializeGicV3)
>> +
>> +/* Initialize GICv3 */
>> +ASM_PFX(InitializeGicV3):
>> +  // In order to setup NS side we need to enable it first.
>> +  mrs     x0, scr_el3
>> +  orr     x0, x0, #1
>> +  msr     scr_el3, x0
>> +
>> +  // Enable SRE at EL3 and ICC_SRE_EL2 access
>> +  mov     x0, #((1 << 3) | (1 << 0))      // Enable | SRE
>> +  mrs     x1, ICC_SRE_EL3
>> +  orr     x1, x1, x0
>> +  msr     ICC_SRE_EL3, x1
>> +  isb
>> +
>> +  // Enable SRE at EL2 and ICC_SRE_EL1 access..
>> +  mrs     x1, ICC_SRE_EL2
>> +  orr     x1, x1, x0
>> +  msr     ICC_SRE_EL2, x1
>> +  isb
>> +
>> +  // Configure CPU interface
>> +  msr     ICC_CTLR_EL3, xzr
>> +  isb
>> +  msr     ICC_CTLR_EL1, xzr
>> +  isb
>> +
>> +  // The MemoryMap view and Register view may not be consistent, So Set PMR again.
>> +  mov     w1, #1 << 7                        // allow NS access to GICC_PMR
>> +  msr     ICC_PMR_EL1, x1
>> +  isb
>> +
>> +  // Remove the SCR.NS bit
>> +  mrs     x0, scr_el3
>> +  and     x0, x0, #~SCR_NS
>> +  msr     scr_el3, x0
>> +  ret
>> diff --git a/CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf b/CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
>> new file mode 100644
>> index 0000000..1603ed1
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
>> @@ -0,0 +1,44 @@
>> +#/* @file
>> +#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
>> +#  Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +#
>> +#  This program and the accompanying materials
>> +#  are licensed and made available under the terms and conditions of the BSD License
>> +#  which accompanies this distribution.  The full text of the license may be found at
>> +#  http://opensource.org/licenses/bsd-license.php
>> +#
>> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +#*/
>> +
>> +[Defines]
>> +  INF_VERSION                    = 1.25
>> +  BASE_NAME                      = CadenceCspSecLib
>> +  FILE_GUID                      = 07a2577e-43fb-40d9-9833-415cb7feefab
>> +  MODULE_TYPE                    = BASE
>> +  VERSION_STRING                 = 1.0
>> +  LIBRARY_CLASS                  = ArmPlatformSecLib
>> +
>> +[Packages]
>> +  ArmPkg/ArmPkg.dec
>> +  ArmPlatformPkg/ArmPlatformPkg.dec
>> +  EmbeddedPkg/EmbeddedPkg.dec
>> +  MdeModulePkg/MdeModulePkg.dec
>> +  MdePkg/MdePkg.dec
>> +
>> +[LibraryClasses]
>> +  IoLib
>> +  ArmLib
>> +  SerialPortLib
>> +
>> +[Sources.common]
>> +  CspSec.c
>> +
>> +[Sources.AARCH64]
>> +  AArch64/CspBoot.S
>> +  AArch64/GicV3.S
>> +
>> +[FixedPcd]
>> +  gArmTokenSpaceGuid.PcdFvBaseAddress
>> +  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
>> diff --git a/CadencePkg/Library/CadenceCspSecLib/CspSec.c b/CadencePkg/Library/CadenceCspSecLib/CspSec.c
>> new file mode 100644
>> index 0000000..7ef45c0
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspSecLib/CspSec.c
>> @@ -0,0 +1,79 @@
>> +/** @file
>> +*
>> +*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
>> +*  Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +*
>> +*  This program and the accompanying materials
>> +*  are licensed and made available under the terms and conditions of the BSD License
>> +*  which accompanies this distribution.  The full text of the license may be found at
>> +*  http://opensource.org/licenses/bsd-license.php
>> +*
>> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +**/
>> +
>> +#include <Library/ArmGicLib.h>
>> +#include <Library/ArmPlatformLib.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/PcdLib.h>
>> +
>> +// Initialize GICv3
>> +VOID
>> +InitializeGicV3 (
>> +  VOID
>> +  );
>> +
>> +/**
>> +  Initialize the Secure peripherals and memory regions
>> +
>> +  If Trustzone is supported by your platform then this function makes the required initialization
>> +  of the secure peripherals and memory regions.
>> +
>> +**/
>> +VOID
>> +ArmPlatformSecTrustzoneInit (
>> +  IN  UINTN                     MpId
>> +  )
>> +{
>> +  // No TZPC or TZASC on RTSM to initialize
>> +}
>> +
>> +/**
>> +  Initialize controllers that must setup at the early stage
>> +
>> +  Some peripherals must be initialized in Secure World.
>> +  For example, some L2x0 requires to be initialized in Secure World
>> +
>> +**/
>> +RETURN_STATUS
>> +ArmPlatformSecInitialize (
>> +  IN  UINTN                     MpId
>> +  )
>> +{
>> +  // If it is not the primary core then there is nothing to do
>> +  if (!ArmPlatformIsPrimaryCore (MpId)) {
>> +    return RETURN_SUCCESS;
>> +  }
>> +
>> +  InitializeGicV3 ();
>> +
>> +  return RETURN_SUCCESS;
>> +}
>> +
>> +/**
>> +  Call before jumping to Normal World
>> +
>> +  This function allows the firmware platform to do extra actions before
>> +  jumping to the Normal World
>> +
>> +**/
>> +VOID
>> +ArmPlatformSecExtraAction (
>> +  IN  UINTN         MpId,
>> +  OUT UINTN*        JumpAddress
>> +  )
>> +{
>> +  *JumpAddress = PcdGet64 (PcdFvBaseAddress);
>> +}
>> --
>> 2.2.2
>>