From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::241; helo=mail-it0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x241.google.com (mail-it0-x241.google.com [IPv6:2607:f8b0:4001:c0b::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AEF6120972143 for ; Thu, 12 Jul 2018 07:35:37 -0700 (PDT) Received: by mail-it0-x241.google.com with SMTP id j185-v6so7080982ite.1 for ; Thu, 12 Jul 2018 07:35:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=yB3EXdWvHwYGhzMgBW5z7UeEhWdzRv6BCeNHG+MscCI=; b=fk1Mmsly4/4F5PHn/4m9Dl/uL1BJKh+weMchzRzCnV5I2vc4hIIhJlQ3rWOwPWhE8p DqIRRVc61NUGEaAvFHNYG3IBAngagV+BWMcJP6yBwlxvZhRZ+Xd6K0a63Edgy8U+401R MjIhePHkKNFGvFvGoW3WCCUtpKjjOopzM0CYk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=yB3EXdWvHwYGhzMgBW5z7UeEhWdzRv6BCeNHG+MscCI=; b=An8o3Rt9yTY67lb/fnm0r9kp2spYMEKMdOmGXhaD33nRuh2Aw/njv3IdmsEQFtupcO meM7oNMi5eY5JDbdGMYC7JKBdYPtAhoMxqcx1fUsq8cFIY4yuh+98Qn+5i7vOBOYxQ6f /G1ykeAOy0rnui6KXK/vp1SRjMdwi9AGcfpIFTE+G4ykJ4xG1bgyffJr84YIVVYDposd T2pLeerHx3WZ/wZMKwzZGubJLQQiDGVhEC/IkGRxv8JAeT9dc0bVUxI8FCS+GInZddDG cjWSoqAqqhAtEDB0UitkKwpHXfB60frpQMgmbmo00reNmam+FVMduGVH0DY9EPOv+tF0 qxxA== X-Gm-Message-State: AOUpUlGi/fSbtva4BDbeGFTBsNRlVaTEqnEuiuE4m+Ls08VOA//AWQlI JbjWcGkvWcuUOYvG0YCsz7V5jIiiZTxxV+/NBkrAPA== X-Google-Smtp-Source: AAOMgpdE/CSTi9mau+hVSNYA+DFIOIqwAZZfeeLc4A4S74Ki68UBaBggJyX8/+Oth2r5MhWJboWn3EjvHy59QXqJHSI= X-Received: by 2002:a02:35a:: with SMTP id y87-v6mr1770395jad.2.1531406136714; Thu, 12 Jul 2018 07:35:36 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:bbc7:0:0:0:0:0 with HTTP; Thu, 12 Jul 2018 07:35:36 -0700 (PDT) In-Reply-To: <1531381201-5022-3-git-send-email-mw@semihalf.com> References: <1531381201-5022-1-git-send-email-mw@semihalf.com> <1531381201-5022-3-git-send-email-mw@semihalf.com> From: Ard Biesheuvel Date: Thu, 12 Jul 2018 16:35:36 +0200 Message-ID: To: Marcin Wojtas Cc: "edk2-devel@lists.01.org" , Leif Lindholm , Nadav Haklai , Hanna Hawa , =?UTF-8?B?SmFuIETEhWJyb8Wb?= , Grzegorz Jaszczyk Subject: Re: [platforms: PATCH 2/6] Marvell/Library: Introduce ArmadaIcuLib class X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jul 2018 14:35:37 -0000 Content-Type: text/plain; charset="UTF-8" On 12 July 2018 at 09:39, Marcin Wojtas wrote: > ICU (Interrupt Consolidation Unit) is a mechanism, > that allows to send a message-based interrupts from the > CP110 unit (South Bridge) to the Application Processor > hardware block. After dispatching the interrupts in the > GIC are generated. > > This patch adds a basic version of the library, that > allows to configure a static mapping between CP110 > interfaces and GIC. It is required for the cases, where > the OS does not support the ICU controller on its own > (e.g. ACPI boot). > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > --- > Silicon/Marvell/Marvell.dec | 1 + > Silicon/Marvell/Include/Library/ArmadaIcuLib.h | 45 ++++++++++++++++++++ > 2 files changed, 46 insertions(+) > create mode 100644 Silicon/Marvell/Include/Library/ArmadaIcuLib.h > > diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec > index 4def897..616624e 100644 > --- a/Silicon/Marvell/Marvell.dec > +++ b/Silicon/Marvell/Marvell.dec > @@ -61,6 +61,7 @@ > > [LibraryClasses] > ArmadaBoardDescLib|Include/Library/ArmadaBoardDescLib.h > + ArmadaIcuLib|Include/Library/ArmadaIcuLib.h > ArmadaSoCDescLib|Include/Library/ArmadaSoCDescLib.h > SampleAtResetLib|Include/Library/SampleAtResetLib.h > > diff --git a/Silicon/Marvell/Include/Library/ArmadaIcuLib.h b/Silicon/Marvell/Include/Library/ArmadaIcuLib.h > new file mode 100644 > index 0000000..9b68934 > --- /dev/null > +++ b/Silicon/Marvell/Include/Library/ArmadaIcuLib.h > @@ -0,0 +1,45 @@ > +/** > +* > +* Copyright (C) 2018, Marvell International Ltd. and its affiliates > +* > +* This program and the accompanying materials are licensed and made available > +* under the terms and conditions of the BSD License which accompanies this > +* distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > +#ifndef __ARMADA_ICU_LIB_H__ > +#define __ARMADA_ICU_LIB_H__ > + > +typedef enum { > + Level = 0, > + Edge = 1 Could we have more discriminating identifiers here please? IcuIrqTypeLevel and IcuIrqTypeEdge perhaps? > +} ICU_IRQ_TYPE; > + > +typedef struct { > + UINTN IcuId; > + UINTN SpiId; > + ICU_IRQ_TYPE IrqType; > +} ICU_IRQ; > + > +typedef struct { > + const ICU_IRQ *Map; > + UINTN Size; > +} ICU_CONFIG_ENTRY; > + > +typedef struct { > + ICU_CONFIG_ENTRY NonSecure; > + ICU_CONFIG_ENTRY Sei; > + ICU_CONFIG_ENTRY Rei; > +} ICU_CONFIG; > + > +EFI_STATUS > +EFIAPI > +ArmadaIcuInitialize ( > + VOID > + ); > + > +#endif /* __ARMADA_ICU_LIB_H__ */ > -- > 2.7.4 >