From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::242; helo=mail-io0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x242.google.com (mail-io0-x242.google.com [IPv6:2607:f8b0:4001:c06::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5EC9D203564D4 for ; Tue, 28 Nov 2017 05:49:28 -0800 (PST) Received: by mail-io0-x242.google.com with SMTP id z74so910228iof.12 for ; Tue, 28 Nov 2017 05:53:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=Y78hQG+VLgR0UYMeUJeMLIlEk/rkAj6dCjKQiAWLLL0=; b=UKsl+t5T8XrUI018mihalKj0TyX/CtSBuWJL18sec95UldcYsuvWSsfWsGSbN89Nog 36/CjbvPh4RmPyTXmEGJZux8nRL4WEQ17FaEIIB8P5c7LKB9FYKbBikhfpCH0mfk5Kfz Cp4cDtVA+0YZOmS5MRLKkPxrC65eeT2JE9Geo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=Y78hQG+VLgR0UYMeUJeMLIlEk/rkAj6dCjKQiAWLLL0=; b=r05NVO6ahLSGtbaW/+xr0NIpQo0Bx1dcBzqIAEfXSHKq/lvL96V+dtZmqPLLN7H4XF WeBccwJOPjo+zNvjG6fEBkjPeBimLuVKdubnJ3s/T1P2z8Xe4cJZot425xmTizHrHx22 X64hxZAc1keq2O+9ka9WhvZiapFcVZm7XGjGWSffDPCKsKsew0XXfLdwu9jbjoC3khkv SFiulMv80ZNKqTv1JtEhUkK7y7v4MoUqZNJlXEMibNUutZ38xSjTtb2bz6xU3vQ0s70l po6mmKnYvE1d8gLpsaVTfeSDDHlHRsal+D4Vd1CIFVWi+VsAGL6f2PFabY9duM5p/Qju BmwQ== X-Gm-Message-State: AJaThX4ZLu0WyBBiI7G4V462mID/63ZSRJwgD/Fsv3wRRQ7AEEoDB4sd ANIDKjKXiVuSerxYGcGrKBc/1icUHGU3OMo6/iuFphOI X-Google-Smtp-Source: AGs4zMa7eC44334HTRIQIbjes32Bh40EQphGOiREMvPMTt74hGuGGk3MnfUxDfc3PHQcVJIqyppLtjDFVKBuzFQz8/g= X-Received: by 10.107.174.222 with SMTP id n91mr5108073ioo.43.1511877230598; Tue, 28 Nov 2017 05:53:50 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.104.16 with HTTP; Tue, 28 Nov 2017 05:53:49 -0800 (PST) In-Reply-To: <20171128134951.ah5rkkes5wx6leu6@bivouac.eciton.net> References: <20171128132807.16701-1-ard.biesheuvel@linaro.org> <20171128134951.ah5rkkes5wx6leu6@bivouac.eciton.net> From: Ard Biesheuvel Date: Tue, 28 Nov 2017 13:53:49 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Daniel Thompson , masahisa.kojima@socionext.com, =?UTF-8?B?UGlwYXQv44Oh44K/44Ov44OL44OD44OI44Od44OzIOODlOODkeODg+ODiA==?= Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Nov 2017 13:49:28 -0000 Content-Type: text/plain; charset="UTF-8" On 28 November 2017 at 13:49, Leif Lindholm wrote: > On Tue, Nov 28, 2017 at 01:37:20PM +0000, Ard Biesheuvel wrote: >> On 28 November 2017 at 13:28, Ard Biesheuvel wrote: >> > As it turns out, it is surprisingly easy to configure both the NETSEC >> > and eMMC devices as cache coherent for DMA, given that they are both >> > behind the same SMMU which is already configured in passthrough mode. > > Configures in passthrough mode by edk2 or earlier firmware? > No, it is the CM3 firmware that configures the various SMMUs on this platform. >> > So update the static SMMU configuration to make memory accesses performed >> > by these devices inner shareable, inner/outer writeback cacheable, which >> > makes them cache coherent with the CPUs. >> > >> > Contributed-under: TianoCore Contribution Agreement 1.1 >> > Signed-off-by: Ard Biesheuvel >> > --- >> > Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 2 +- >> > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 ++ >> > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 2 +- >> > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 23 ++++++++++++++++++++ >> > Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++++ >> > Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 3 +++ >> > 6 files changed, 34 insertions(+), 2 deletions(-) >> > >> > diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc >> > index 7245240012bc..dd4a7f9baf69 100644 >> > --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc >> > +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc >> > @@ -597,7 +597,7 @@ [Components.common] >> > NetworkPkg/HttpBootDxe/HttpBootDxe.inf >> > Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf { >> > >> > - DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf >> > + DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf >> > } >> > >> > # >> >> Note: this hunk ^^^ needs to be applied to DeveloperBox.dsc as well. > > Do I wait for a v2 including that? > Would you like me to? I added this for Daniel and/or Masami, in case they were intending to test this patch. I'd like to get confirmation from them or others that this works as expected before merging this, so there is no rush. -- Ard.