From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-it0-x236.google.com (mail-it0-x236.google.com [IPv6:2607:f8b0:4001:c0b::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 54BE781EC7 for ; Tue, 15 Nov 2016 09:03:24 -0800 (PST) Received: by mail-it0-x236.google.com with SMTP id o1so10014336ito.1 for ; Tue, 15 Nov 2016 09:03:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=Bv76ukPnl1k0mXX+wn5BsaIZHpZz0YXG+GDCU/zQU2s=; b=h/3FRvGS0Ce5izP9Zm+pGskcoR/ANSw8g17aISeZjxdNe1pMnz9e88iuRcBVzuOFqW Z5ji+EI+zkF3LLeIn4z8pUwuq1FTWe7ugzZH/WSJWBBhzjJOOkPEIXmbyKPFIYZ/e/m3 2BAorA18lE9fQDVqiXgPksRFSDu6tkc2Vh6qk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=Bv76ukPnl1k0mXX+wn5BsaIZHpZz0YXG+GDCU/zQU2s=; b=bE9ykfLvQEfWICXDse4OMwkouuu3ax/sC5yuBBi16MvxytE6nYVcFid/Y9yd/acTq1 UHVEjl/7pL2Bj+z7R+hXbEJjmNhVkF+r1Kzqs3ZEo7XYx2PWDRKC8+deqcNBItCQ1SL5 8m8YQxG+jC8YPpCdah4vvO6QIpd9WUQkU4kix8InGPxsDU3xGNPgGxsN1NUb/epbPhxh c4yPYjOoDC6iQe8l9/FOvtDUJCuHlDxtSfBvUIVj8iH44En9P4qQlNRZAhEHrwAxKV/S h1OI8aKuh00Vm+Sf/CvhuC2A+QUiTYF13jI7DWfZHZb6QQWhusRRE6i+41LrWNpQbld7 TYBQ== X-Gm-Message-State: ABUngvcdYszINSYSpGm4WYRQP8MofORE8IatOZuuQdp+YdFl9KEBSzdJJyh1e/qUqtfo9d1QsEy4zEOw1VGng5e1 X-Received: by 10.36.14.131 with SMTP id 125mr3781562ite.59.1479229377328; Tue, 15 Nov 2016 09:02:57 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.59.147 with HTTP; Tue, 15 Nov 2016 09:02:56 -0800 (PST) In-Reply-To: <5b3a4799-78b4-3616-31c1-feafe002833f@arm.com> References: <1479157789-14674-1-git-send-email-jeremy.linton@arm.com> <1479157789-14674-4-git-send-email-jeremy.linton@arm.com> <5b3a4799-78b4-3616-31c1-feafe002833f@arm.com> From: Ard Biesheuvel Date: Tue, 15 Nov 2016 17:02:56 +0000 Message-ID: To: Jeremy Linton Cc: edk2-devel-01 , Steve Capper , Leif Lindholm , Ryan Harkin , linaro-uefi Subject: Re: [PATCH 3/7] EmbeddedPkg: SiI3132: Add SCSI protocol support to header X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 Nov 2016 17:03:24 -0000 Content-Type: text/plain; charset=UTF-8 On 14 November 2016 at 21:24, Jeremy Linton wrote: > On 11/14/2016 03:09 PM, Jeremy Linton wrote: >> >> Add EXT_SCSI_PASS_THRU structures to SI3132_PORT structure, >> along with helpers and new entry points. > > > Of course, I noticed after posting that this patch is missing a prereq, that > should have been squashed into it. > > (see below) > > >> >> Contributed-under: TianoCore Contribution Agreement 1.0 >> Signed-off-by: Jeremy Linton >> --- >> EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h | 89 >> +++++++++++++++++++++++- >> 1 file changed, 87 insertions(+), 2 deletions(-) >> >> diff --git a/EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h >> b/EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h >> index f23446a..91f9448 100644 >> --- a/EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h >> +++ b/EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h >> @@ -20,6 +20,7 @@ >> >> #include >> #include >> +#include >> >> #include >> #include >> @@ -57,6 +58,7 @@ >> #define SII3132_PORT_SLOTSTATUS_REG 0x1800 >> #define SII3132_PORT_CMDACTIV_REG 0x1C00 >> #define SII3132_PORT_SSTATUS_REG 0x1F04 >> +#define SII3132_PORT_SERROR_REG 0x1F08 >> >> #define SII3132_PORT_CONTROL_RESET (1 << 0) >> #define SII3132_PORT_DEVICE_RESET (1 << 1) >> @@ -81,6 +83,7 @@ >> #define PRB_CTRL_INT_MASK 0x40 >> #define PRB_CTRL_SRST 0x80 >> >> +#define PRB_PROT_DEFAULT 0x00 >> #define PRB_PROT_PACKET 0x01 >> #define PRB_PROT_LEGACY_QUEUE 0x02 >> #define PRB_PROT_NATIVE_QUEUE 0x04 >> @@ -88,6 +91,9 @@ >> #define PRB_PROT_WRITE 0x10 >> #define PRB_PROT_TRANSPARENT 0x20 >> >> +#define SII_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device >> +#define SII_FIS_CONTROL_CMD (1 << 7) //Indicate FIS is a command >> + >> #define SGE_XCF (1 << 28) >> #define SGE_DRD (1 << 29) >> #define SGE_LNK (1 << 30) >> @@ -95,7 +101,7 @@ >> >> #define SI_MAX_CDB 12 //MAX supported CDB >> #define SI_MAX_SENSE 256 >> -#define SI_DEFAULT_TIMEOUT 20000 >> +#define SI_DEFAULT_TIMEOUT 50000 > > > > Right here this is wrong, all three of these lines should be new > > SI_MAX_CDB, SI_MAX_SENSE and SI_DEFAULT_TIMEOUT all need to be declared. > WIth this fixed (and the redundant newlines removed, especially inside struct definitions) Reviewed-by: Ard Biesheuvel > >> >> >> typedef struct _SATA_SI3132_SGE { >> @@ -126,6 +132,8 @@ typedef struct _SATA_SI3132_DEVICE { >> UINTN Index; >> struct _SATA_SI3132_PORT *Port; //Parent Port >> UINT32 BlockSize; >> + BOOLEAN Atapi; //ATAPI device >> + BOOLEAN Cdb16; //Uses 16byte CDB transfers (or >> 12) >> } SATA_SI3132_DEVICE; >> >> typedef struct _SATA_SI3132_PORT { >> @@ -146,13 +154,18 @@ typedef struct _SATA_SI3132_INSTANCE { >> >> SATA_SI3132_PORT Ports[SATA_SII3132_MAXPORT]; >> >> - EFI_ATA_PASS_THRU_PROTOCOL AtaPassThruProtocol; >> + EFI_ATA_PASS_THRU_MODE AtaPassThruMode; >> + EFI_ATA_PASS_THRU_PROTOCOL AtaPassThruProtocol; >> + EFI_EXT_SCSI_PASS_THRU_MODE ExtScsiPassThruMode; >> + EFI_EXT_SCSI_PASS_THRU_PROTOCOL ExtScsiPassThru; >> + >> >> EFI_PCI_IO_PROTOCOL *PciIo; >> } SATA_SI3132_INSTANCE; >> >> #define SATA_SII3132_SIGNATURE SIGNATURE_32('s', 'i', '3', >> '2') >> #define INSTANCE_FROM_ATAPASSTHRU_THIS(a) CR(a, SATA_SI3132_INSTANCE, >> AtaPassThruProtocol, SATA_SII3132_SIGNATURE) >> +#define INSTANCE_FROM_SCSIPASSTHRU_THIS(a) CR(a, SATA_SI3132_INSTANCE, >> ExtScsiPassThru, SATA_SII3132_SIGNATURE) >> >> #define SATA_GLOBAL_READ32(Offset, Value) PciIo->Mem.Read (PciIo, >> EfiPciIoWidthUint32, 0, Offset, 1, Value) >> #define SATA_GLOBAL_WRITE32(Offset, Value) { UINT32 Value32 = Value; >> PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, &Value32); } >> @@ -271,4 +284,76 @@ EFI_STATUS SiI3132ResetDevice ( >> IN UINT16 PortMultiplierPort >> ); >> >> +/** >> + * EFI ATA Pass Thru Entry points for SCSI Protocol >> + */ >> +SATA_SI3132_DEVICE* GetSataDevice ( >> + IN SATA_SI3132_INSTANCE *SataInstance, >> + IN UINT16 Port, >> + IN UINT16 PortMultiplierPort >> + ); >> + >> + >> +EFI_STATUS SiI3132IssueCommand( >> + IN SATA_SI3132_PORT *SataPort, >> + EFI_PCI_IO_PROTOCOL *PciIo, >> + IN UINT32 Timeout, >> + VOID *StatusBlock >> + ); >> + >> + >> + >> +/** >> + * EFI SCSI Pass Thru Protocol >> + */ >> +EFI_STATUS SiI3132ScsiPassThru( >> + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, >> + IN UINT8 *Target, >> + IN UINT64 Lun, >> + IN OUT EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet, >> + IN EFI_EVENT Event OPTIONAL >> + ); >> + >> +EFI_STATUS SiI3132GetNextTargetLun( >> + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, >> + IN OUT UINT8 **Target, >> + IN OUT UINT64 *Lun >> +); >> + >> +EFI_STATUS SiI3132GetNextTargetLun2( >> + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, >> + IN UINT8 *Target, >> + IN UINT64 Lun, >> + IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath >> + ); >> + >> +EFI_STATUS SiI3132ScsiBuildDevicePath( >> + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, >> + IN UINT8 *Target, >> + IN UINT64 Lun, >> + IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath >> + ); >> + >> +EFI_STATUS SiI3132GetTargetLun ( >> + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, >> + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, >> + OUT UINT8 **Target, >> + OUT UINT64 *Lun >> + ); >> + >> +EFI_STATUS SiI3132ResetChannel( >> + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This >> + ); >> + >> +EFI_STATUS SiI3132ResetTargetLun( >> + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, >> + IN UINT8 *Target, >> + IN UINT64 Lun >> + ); >> + >> +EFI_STATUS SiI3132GetNextTarget( >> + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, >> + IN OUT UINT8 **Target >> + ); >> + >> #endif >> > > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel