From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-it0-x232.google.com (mail-it0-x232.google.com [IPv6:2607:f8b0:4001:c0b::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 914391A1EBD for ; Wed, 21 Sep 2016 10:20:48 -0700 (PDT) Received: by mail-it0-x232.google.com with SMTP id 186so57261928itf.0 for ; Wed, 21 Sep 2016 10:20:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=nE02mHR5qlXn0ltqbBDjsQx7PXFtHqsdAhs/ShkqQWg=; b=kOwPsB5o2LWyGQe/2r/ynnSPD2LN8pr0telm4CWE6oULoLH5c8WZrT3ut/L2IwEQ2z VqNaVstSmr0HErDbRjcZYrBK0wyO2rOHlT0NWb9mNXnk0WMFSbOGjEcEKC+t6/WjErgM CVMyi/8nMeVCrT41SLegvwLaG/GCK47ZGCz0s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=nE02mHR5qlXn0ltqbBDjsQx7PXFtHqsdAhs/ShkqQWg=; b=Zkdig38hTHod5K2bH35WOvFIE6QQZB/i3q74sDbFdB1SXUrOYEwsasFP2zBQ04ZyzO ZTYMpv82TgQ4Tlc8W0LH3aHL1E7hedPhbE/5do3lBj9Zm3U8Ml3qvSppxXRharcNt41U 1cPA9BinjcXLixffqOnWO2AfN2gFw4UvjAiQfqXM89rtWVyHcTtbZe/Q/nD3IA7JGzHf 9A4Ze8OJ9GDe19Hn5N8rqFEUW+8MQwQOFWLgNxjIU1HZC60yKbZkvvu+WFDraQ/6hau1 4LZAdfdDWDq464pOn5RDNrhqVjcm95f+Cmv2nKD1opT1UNjuflolRsMpieocHhFkTq7y k8hA== X-Gm-Message-State: AE9vXwMk/am77d56Myb4bG9CsJC+11StUUwvrzLcnLFvSxJrNtxwN/LCEo5z0v0WqQ+18hY8GDbD8cICsVnDdUfI X-Received: by 10.36.209.196 with SMTP id w187mr5359231itg.47.1474478447699; Wed, 21 Sep 2016 10:20:47 -0700 (PDT) MIME-Version: 1.0 Received: by 10.36.204.195 with HTTP; Wed, 21 Sep 2016 10:20:47 -0700 (PDT) In-Reply-To: References: From: Ard Biesheuvel Date: Wed, 21 Sep 2016 18:20:47 +0100 Message-ID: To: Kurt Kennett Cc: edk2-devel Subject: Re: Problem with Arm Mmu code in CpuDxe X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Sep 2016 17:20:48 -0000 Content-Type: text/plain; charset=UTF-8 On 21 September 2016 at 17:09, Kurt Kennett wrote: > I am having a problem on my system (assert), and during investigation I may have found a problem with the Arm CpuDxe Mmu code that may affect all ARM platform users. > > CpuDxeInitialize is the entry point, and pretty soon after entry it does: > > SyncCacheConfig (&mCpu); > > This calls into: > ArmPkg\Drivers\CpuDxe\Arm\Mmu.c > > The code asserts that the Mmu is enabled, gets the memory space map, then starts to process the page tables by getting the TTBR0 base address. Before the assert, there is a comment that says // This code assumes MMU is enabled and filed [sic] with section translations I don't know if this is a reasonable thing to assume, and how you end up violating this assumption, but it does explain why the code does not work correctly. What does your memory map look like?