From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw0-x230.google.com (mail-yw0-x230.google.com [IPv6:2607:f8b0:4002:c05::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EB6F61A1E3B for ; Mon, 24 Oct 2016 09:16:45 -0700 (PDT) Received: by mail-yw0-x230.google.com with SMTP id u124so4161217ywg.3 for ; Mon, 24 Oct 2016 09:16:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=B0DV9bQzmMEXU1ezQ3r8WN4SikUXT3SzV0syRPAxQYw=; b=VoYZLBKeVzgrB9WYvrQcNkk7uZfT9n+5+oJ8vXkqcNNEen91bYC6TZNEICR7lGUtf3 X/BMNhhUOAzaxZEVfDVrRJDqKMCyRZnynuiJBNyQmM3Wg2LM78FCEp/aduZgQHuxRXAF DmMsp/TU5Xtw4PjcPt51C9LHavLJ7/hQ0AUSU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=B0DV9bQzmMEXU1ezQ3r8WN4SikUXT3SzV0syRPAxQYw=; b=g5SUka/+6lWXppkRlHLblSxMVLNHHuRZlhTgkrJ8PMneoefcoMhKrxK4QBj8k3CdbE ob3ZTQg8Uloue9gyZFMqJdXt4YH1TPAuzQNGhLeHjO4sOowt+Gxv21XztDF5b65741wB q+Y3dS8/tDgKVaR3qx/BmkQwWq6PLrJ46iI8yOx9mqicchenrKvs+OavUcWtN02UrO1K +AHTuwyFQc9/yKbFp1DoDJSoMPR6lkdrNjxbeOxWt92Us0KCi+vt5X+xyTU6zuxQopQp fg2NqbrkSq76HXdTprtq60u7584U21r0UBp+M/fAfMrufgdcdSY3hq8SqxxgKYdpQCqC 61yQ== X-Gm-Message-State: ABUngvd5KxFjIi37NHsM0xqjNU/MhjM75cZO+qC/OuXZvangCveNmVtlHTAtyXR6NDGnofl3bctsxbC7eMohTV1x X-Received: by 10.107.2.65 with SMTP id 62mr12775252ioc.83.1477325805161; Mon, 24 Oct 2016 09:16:45 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.5.139 with HTTP; Mon, 24 Oct 2016 09:16:44 -0700 (PDT) In-Reply-To: References: <1477278296-24809-1-git-send-email-dennis.chen@arm.com> From: Ard Biesheuvel Date: Mon, 24 Oct 2016 17:16:44 +0100 Message-ID: To: Ryan Harkin Cc: Dennis Chen , edk2-devel-01 , nd@arm.com, Laszlo Ersek , Leif Lindholm Subject: Re: [PATCH] ARMPkg: Unified the GIC base address variables as 64-bit width X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 24 Oct 2016 16:16:46 -0000 Content-Type: text/plain; charset=UTF-8 On 24 October 2016 at 12:47, Ryan Harkin wrote: > On 24 October 2016 at 04:04, Dennis Chen wrote: >> Since ACPI spec defines the GIC base addresses (CPU interface, >> Distributor and Redistributor*GICv3 only*) as 64-bit, so we should >> define these corresponding base address variables as 64-bit instead of >> 32-bit. This patch redefines them according to the ACPI spec. >> > > Following on with Ard's comment on the earlier version, what happens > if you want to use GICv3 on a 32bit system, eg the Cortex-A32 FVP > models, which I believe [1] has GICv3? > I don't think that matters. GICv3 does not use MMIO for the CPU interface anyway, and referring to the MMIO bits using 64-bit types is unlikely to affect performance imo. From a functionality pov, those top bits will simply be always zero (much like they are now on every known ARM platform) > [1] Go here and search for "gicv3" > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0834i/Chunk1955773768.html >