From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::d43; helo=mail-io1-xd43.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd43.google.com (mail-io1-xd43.google.com [IPv6:2607:f8b0:4864:20::d43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E82512115F527 for ; Fri, 12 Oct 2018 09:24:29 -0700 (PDT) Received: by mail-io1-xd43.google.com with SMTP id e12-v6so9602834iok.12 for ; Fri, 12 Oct 2018 09:24:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=l6sqbQhUum+LkU6NhWR1Ig+g9Bko+CbK40Qup+Y+iCk=; b=fifzwNzhDqQPWF7htc61m0QJ5k7fgo+CYVHPH8ClApwhx5gdWvPcKhZaps6AL2DVR0 sCDLcks4ByZ2sOf6Iobj114ZEThOx+NVkNqLow3CTGae6KSF/0n2qZm0wcXOD5bEd6Sk N5f7XKtuk98+ElmrQnGAEp7ZAlTxDqOPAscdk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=l6sqbQhUum+LkU6NhWR1Ig+g9Bko+CbK40Qup+Y+iCk=; b=tdCEf5UFQSPQe4KzdKra/U3IhhaUBgJ29bhfhi8CDH6GhwwSupGNj6NZQVtvNZ+Mff /iWwA17VU+Vp1liOKlXFan/xMHXwk+b7FIwYq3x5DIfpEsKjMEibrPnjAmy4oDK2g1WH wsTepWaNAeBJa9L4jGgEkBYldN1oj6M8ZfMd7vtFw37GqQEorj6Tu45JJserxJXCXFXQ 1wnPoa3VwtTx1BUh2ZpicuA8KvtMgDRqMIZSL266v8/WC1oAw9YiTCvBZtSIluNJJI6T ntuOdGBl2ritZcmNw/iduJma98m1tUMIbf7c1IxCSKAbp60NedWCUa4blhYcBigBG/3o 7nRg== X-Gm-Message-State: ABuFfoilaBmlSDIuUBs2HCw0PnYujZgksumm+GZf/cttZs7mvoIicwG5 Uk2IvptYaNN33uJSKH3XJDb6glfC/TR0amJ4ywxvdg== X-Google-Smtp-Source: ACcGV61ItHL1OzUd4GWz21XGkzFKgSDT/1LujNuFR08m80Tdb8ohAwIzD+OPgSH6tn4J/3RCns4nuiRHvYDOLPI0IHs= X-Received: by 2002:a6b:5d12:: with SMTP id r18-v6mr4503879iob.170.1539361468899; Fri, 12 Oct 2018 09:24:28 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:5910:0:0:0:0:0 with HTTP; Fri, 12 Oct 2018 09:24:27 -0700 (PDT) In-Reply-To: References: <1538745911-22484-1-git-send-email-mw@semihalf.com> <1538745911-22484-3-git-send-email-mw@semihalf.com> From: Ard Biesheuvel Date: Fri, 12 Oct 2018 18:24:27 +0200 Message-ID: To: Marcin Wojtas Cc: "Gao, Liming" , "Kinney, Michael D" , "Ni, Ruiyu" , "Tian, Feng" , Tomasz Michalec , "Zeng, Star" , edk2-devel-01 , Eric Dong , "Wu, Hao A" , Nadav Haklai Subject: Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Oct 2018 16:24:30 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri 12 Oct 2018 at 18:04, Marcin Wojtas wrote: > > pt., 12 pa=C5=BA 2018 o 17:55 Ard Biesheuvel = napisa=C5=82(a): > > > > On 12 October 2018 at 07:06, Marcin Wojtas wrote: > > > pt., 12 pa=C5=BA 2018 o 03:41 Wu, Hao A napisa= =C5=82(a): > > >> > > >> > -----Original Message----- > > >> > From: Marcin Wojtas [mailto:mw@semihalf.com] > > >> > Sent: Thursday, October 11, 2018 11:43 PM > > >> > To: Wu, Hao A > > >> > Cc: Ni, Ruiyu; Ard Biesheuvel; Tian, Feng; Tomasz Michalec; Dong, = Eric; edk2- > > >> > devel-01; Gao, Liming; nadavh@marvell.com; Kinney, Michael D; Zeng= , Star > > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add > > >> > UhsSignaling to SdMmcOverride protocol > > >> > > > >> > wt., 9 pa=C5=BA 2018 o 13:51 Marcin Wojtas napis= a=C5=82(a): > > >> > > > > >> > > wt., 9 pa=C5=BA 2018 o 13:45 Ard Biesheuvel > > >> > napisa=C5=82(a): > > >> > > > > > >> > > > On 9 October 2018 at 13:32, Marcin Wojtas wr= ote: > > >> > > > > wt., 9 pa=C5=BA 2018 o 13:28 Wu, Hao A = napisa=C5=82(a): > > >> > > > >> > > >> > > > >> > -----Original Message----- > > >> > > > >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org]= On > > >> > Behalf Of Ard > > >> > > > >> > Biesheuvel > > >> > > > >> > Sent: Monday, October 08, 2018 11:10 PM > > >> > > > >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A > > >> > > > >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-0= 1; Gao, > > >> > Liming; > > >> > > > >> > Nadav Haklai; Kinney, Michael D; Zeng, Star > > >> > > > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciH= cDxe: > > >> > Add > > >> > > > >> > UhsSignaling to SdMmcOverride protocol > > >> > > > >> > > > >> > > > ... > > >> > > > >> > > > >> > > > >> > I suppose this is defined by the eMMC spec. > > >> > > > >> > > > >> > > > >> > Ruiyu, Hao, could you clarify? Are the host control 2 reg= ister values > > >> > > > >> > for HS200/HS400 defined by the eMMC spec? > > >> > > > >> > > >> > > > >> Hi Ard and Marcin, > > >> > > > >> > > >> > > > >> As far as I know, the EMMC Electrical Standard Spec 5.1 (la= test) does > > >> > not > > >> > > > >> mention on how to set the "UHS Mode Select" field of the Ho= st > > >> > Control 2 > > >> > > > >> Register when switching to HS200/HS400. (Actually, the EMMC= spec > > >> > does not > > >> > > > >> mention Host Control 2 Register at all) > > >> > > > >> > > >> > > > >> When it comes to setting the bus mode for EMMC devices, the= current > > >> > > > >> implementation of the SdMmcPciHcDxe driver does a mapping w= hen > > >> > setting the > > >> > > > >> Host Control 2 Register: > > >> > > > >> > > >> > > > >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single > > >> > > > >> matches > > >> > > > >> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single > > >> > > > >> > > >> > > > >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual > > >> > > > >> matches > > >> > > > >> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual > > >> > > > >> > > >> > > > >> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single > > >> > > > >> matches > > >> > > > >> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single > > >> > > > >> > > >> > > > >> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual > > >> > > > >> matches > > >> > > > >> SD None > > >> > > > >> > > >> > > > >> And there is no obvious counterpart for the EMMC HS400 mode= in the > > >> > SD > > >> > > > >> spec. The driver currently sets the "UHS Mode Select" field= to a > > >> > reserved > > >> > > > >> value 0x5. > > >> > > > >> > > >> > > > > > > >> > > > > Thank you Hao, above is on par with what the default UhsSign= aling > > >> > > > > routine does in this patch. IMO especially in case the EMMC = standard > > >> > > > > is not unequivocal regarding UHS_MODE_SEL, I'd encourage to = accept > > >> > > > > some way of updating HostControl2 register, depending on the > > >> > > > > implementation. What is your opinion Ard? > > >> > > > > > > >> > > > > > >> > > > I would like to know where the current values in SdMmcPciHcDxe= come > > >> > > > from if they are not defined in any spec. > > >> > > > > > >> > > > How do we know which ones are the correct ones? > > >> > > > > >> > > Hao, can you justify used values? > > >> > > > > >> > > > >> > Hi Hao, > > >> > > > >> > Can you please take a look at the UHS_MODE_SEL values source for e= MMC? > > >> > > >> Hi Marcin, > > >> > > >> Sorry for the delayed response. > > >> > > >> For the current implementation of the SdMmcPciHcDxe driver, the sele= cting > > >> of "UHS Mode Select" field value of the Host Control 2 Register is b= ased > > >> on a Max Clock Frequency & Data Rate (Single or Dual) matching > > >> relationship between the: > > >> > > >> A. Table 3-6 of the SD Specifications Part 1 Physical Layer Simplifi= ed > > >> Specification Version 4.10 > > >> > > >> and > > >> > > >> B. Table 4 of the EMMC Electrical Standard Spec 5.1 > > >> > > >> The matching details was included in my previous reply. The only mis= sing > > >> part is there seems no matching for the EMMC HS400 mode in the SD > > >> specifications. For this case, we are currently using the same appro= ach > > >> with the Linux implementation, that is to set the "UHS Mode Select" = to a > > >> value of 0x5 (not standard). > > >> > > > > > > Hao, > > > > > > Thanks a lot for the clarification. > > > > > > Ard, > > > > > > Knowing the numbers details, what is your view of the UhsSignaling ha= ndling? > > > > > > > I think it makes sense to be able to override the SD->MMC mapping for > > HC2 attributes. But it seems to me that this mapping is rather ad-hoc > > and so it should apply to all configuration that is inferred: > > UhsSignalling does not quite cover it. > > > > So I think the approach is correct, but we need a better name. > > Do you mean to update more fields in HC2 than UHS_MODE_SEL? AIUI the EMMC spec does not mention HC2 at all, and yet we have to set it to a sane value, and we are currently using fuzzy logic for it. Or are the other fields less ambiguous?