From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::241; helo=mail-it0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x241.google.com (mail-it0-x241.google.com [IPv6:2607:f8b0:4001:c0b::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6DD8F210C1EC4 for ; Wed, 25 Jul 2018 03:05:00 -0700 (PDT) Received: by mail-it0-x241.google.com with SMTP id d16-v6so8377045itj.0 for ; Wed, 25 Jul 2018 03:05:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=7LWng1xpwa1L+ZEEswV99XwnoGebQ/XqTvgCrpJqKC4=; b=eWcGstH3371JwibUrrCcQMu2LSp7+3uFmJ1LWpdefqVYEgfj2E09PdemfFP+EkIEkN TVdt1eRqgaRBuRtxImMyJkASpUsav6dOqg31v5rQV0MjFhHhXM/AgitGSMTUfSvvTAuU zrWu6zws9uSgETBV+UDNRAf3fveUAk0hBaTS0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=7LWng1xpwa1L+ZEEswV99XwnoGebQ/XqTvgCrpJqKC4=; b=JNWhgtUwUZQUS0VGVf6ukzYYpzT1Hwszi3C5myfzn4sJurI3fj8MhEah0KsJwOhLr5 jmlDHCaqqbBGPEN4xGxXc7tfPLF1IBBI89fscQSAdalHvvuVVlWK9SZV7KahNWw8JmgT bOdVPGWImZGKKwXREbt/Fcg4fwx8iTgX/FwzvKvNRKW417yvath0HkeP+8HGI77lIUX/ UMnIlbvsjLns+YPY+gWoJTLsxMvg+046WoxDUTezzLcKSgNVZP94ppJhsBGiRMuIkebp Kb4MwyFU+VF02J7LFPkt3JV9brAaf7jrmnSOuf0H4LGMmw0zlqklSq7tuoTBRmTpLMGy EiUg== X-Gm-Message-State: AOUpUlFfaeBnYQJqy9xQc6NZSHs9TGRw4nZ0VW5tHgDf6qNF3KotoBrJ PIKSEtLAYoE4Dvm45waLSmyBHuwC+kKYso0lmQV0vw== X-Google-Smtp-Source: AAOMgpepkOhobA6+dPdVw6E9GJ/DcpgTInGYgy+KNPp8dh3GQ+QgL6+TEs9rB45ZVCQLMkxnTDAEnzc9AkTSD6/yh7U= X-Received: by 2002:a02:bb04:: with SMTP id y4-v6mr19314041jan.5.1532513099404; Wed, 25 Jul 2018 03:04:59 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:ac05:0:0:0:0:0 with HTTP; Wed, 25 Jul 2018 03:04:58 -0700 (PDT) In-Reply-To: <1532351961-17377-1-git-send-email-sumit.garg@linaro.org> References: <1532351961-17377-1-git-send-email-sumit.garg@linaro.org> From: Ard Biesheuvel Date: Wed, 25 Jul 2018 12:04:58 +0200 Message-ID: To: Sumit Garg , Daniel Thompson Cc: "edk2-devel@lists.01.org" , Patch Tracking , Leif Lindholm Subject: Re: [PATCH edk2-platforms v2 1/1] Silicon/SynQuacer: add optional OP-TEE DT node X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jul 2018 10:05:00 -0000 Content-Type: text/plain; charset="UTF-8" On 23 July 2018 at 15:19, Sumit Garg wrote: > OP-TEE is optional on Developerbox controlled via SCP firmware. To check > if we need to delete OP-TEE DT node, we use DRAM1 region info as SCP > firmware conditionally carves out Secure memory from DRAM1 region. > > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Sumit Garg > --- > As discussed on IRC, i am not a fan of inferring the presence of OP-TEE from the base/size values of the first DRAM region. Please refer to the existing PCIe code how to read a GPIO in PEI and set a dynamic PCD accordingly, so you can use its value in PlatformDxe. > Changes since v1: > - Add support for optional OP-TEE DT node addition > > Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf | 3 ++ > Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 33 ++++++++++++++++++++ > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 7 +++++ > 3 files changed, 43 insertions(+) > > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf > index 548d62fd5c0a..46cd3f85e509 100644 > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf > @@ -35,6 +35,9 @@ [LibraryClasses] > FdtLib > MemoryAllocationLib > > +[FixedPcd] > + gSynQuacerTokenSpaceGuid.PcdDramInfoBase > + > [Pcd] > gSynQuacerTokenSpaceGuid.PcdPcieEnableMask > gSynQuacerTokenSpaceGuid.PcdPlatformSettings > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c > index 897d06743708..da1209b4a613 100644 > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c > @@ -19,10 +19,13 @@ > #include > #include > #include > +#include > #include > > // add enough space for three instances of 'status = "disabled"' > #define DTB_PADDING 64 > +// base address for OP-TEE used to determine its presence > +#define OPTEE_BASE_ADDR 0xFC000000 > > STATIC > VOID > @@ -47,6 +50,29 @@ DisableDtNode ( > } > } > > +STATIC > +VOID > +DeleteDtNode ( > + IN VOID *Dtb, > + IN CONST CHAR8 *NodePath > + ) > +{ > + INT32 Node; > + INT32 Rc; > + > + Node = fdt_path_offset (Dtb, NodePath); > + if (Node < 0) { > + DEBUG ((DEBUG_ERROR, "%a: failed to locate DT path '%a': %a\n", > + __FUNCTION__, NodePath, fdt_strerror (Node))); > + return; > + } > + Rc = fdt_del_node (Dtb, Node); > + if (Rc < 0) { > + DEBUG ((DEBUG_ERROR, "%a: failed to delete node on '%a': %a\n", > + __FUNCTION__, NodePath, fdt_strerror (Rc))); > + } > +} > + > /** > Return a pool allocated copy of the DTB image that is appropriate for > booting the current platform via DT. > @@ -73,6 +99,7 @@ DtPlatformLoadDtb ( > UINTN CopyDtbSize; > INT32 Rc; > UINT64 SettingsVal; > + DRAM_INFO *DramInfo; > SYNQUACER_PLATFORM_VARSTORE_DATA *Settings; > > Status = GetSectionFromAnyFv (&gDtPlatformDefaultDtbFileGuid, > @@ -107,6 +134,12 @@ DtPlatformLoadDtb ( > DisableDtNode (CopyDtb, "/sdhci@52300000"); > } > > + DramInfo = (VOID *)(UINTN)FixedPcdGet64 (PcdDramInfoBase); > + > + if ((DramInfo->Entry[0].Base + DramInfo->Entry[0].Size) > OPTEE_BASE_ADDR) { > + DeleteDtNode (CopyDtb, "/firmware/optee"); > + } > + > *Dtb = CopyDtb; > *DtbSize = CopyDtbSize; > > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > index 37d642e4b237..d109a5742793 100644 > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > @@ -574,6 +574,13 @@ > #address-cells = <1>; > #size-cells = <0>; > }; > + > + firmware { > + optee { > + compatible = "linaro,optee-tz"; > + method = "smc"; > + }; > + }; > }; > > #include "SynQuacerCaches.dtsi" > -- > 2.7.4 >