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From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date: Thu, 12 Jul 2018 09:58:24 +0200
Message-ID: <CAKv+Gu-zYDi3yg5CifM3mbKTeRR8mhy65nDBVifjMdig5f4ZOg@mail.gmail.com>
To: Marcin Wojtas <mw@semihalf.com>
Cc: "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>,
 Leif Lindholm <leif.lindholm@linaro.org>, 
 Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>, 
 =?UTF-8?B?SmFuIETEhWJyb8Wb?= <jsd@semihalf.com>, 
 Grzegorz Jaszczyk <jaz@semihalf.com>
Subject: Re: [platforms: PATCH 1/6] Marvell/Armada70x0Db: Set correct CP110 count
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On 12 July 2018 at 09:39, Marcin Wojtas <mw@semihalf.com> wrote:
> As a preparation for adding the ICU (Interrupt Consolidation
> Unit) library implementation a correct CP110 count is required.
> Do it for Armada70x0Db and fix depending XHCI/AHCI PCD's accordingly.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> ---
>  Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
> index 5ccee1b..2240a57 100644
> --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
> +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
> @@ -53,6 +53,9 @@
>  #
>  ################################################################################
>  [PcdsFixedAtBuild.common]
> +  #CP110 count
> +  gMarvellTokenSpaceGuid.PcdMaxCpCount|1
> +
>    #MPP
>    gMarvellTokenSpaceGuid.PcdMppChipCount|2
>
> @@ -129,8 +132,8 @@
>    gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
>
>    #PciEmulation
> -  gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 }
> -  gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x0 }
> +  gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
> +  gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 }
>    gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
>
>    #RTC
> --
> 2.7.4
>