From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::241; helo=mail-io0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x241.google.com (mail-io0-x241.google.com [IPv6:2607:f8b0:4001:c06::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 07068209603EB for ; Thu, 31 May 2018 02:17:48 -0700 (PDT) Received: by mail-io0-x241.google.com with SMTP id e15-v6so16619028iog.1 for ; Thu, 31 May 2018 02:17:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=hrRI+l7zFDdE6PZtDfutFWHShGQF6d4jZbwHfGQ5lIU=; b=FW0+0MYoNwncy8Hlhv+UHeGz2lHbn0Zc7T02gzMG+NYlnC4DIcKr057/fEumErCVdW ZoJzLaK2OpDwlscv+KSQr1p3Z+bDWGjDJREsKdxlhaBw29/VlIqDthXlsQCmfxGRnPb3 fel6B+kNmz2j6/hk4LEpN5QcaGj6PrPt8rAvI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=hrRI+l7zFDdE6PZtDfutFWHShGQF6d4jZbwHfGQ5lIU=; b=eL6MxEIcvH/dZhPAG9MjtQYi0u1GSP1EMLhZKQPDM4A8m3JXtgatUh7XOFAoZiMNpy E07bZbuMYhJyHw/nxLfklhaAg2iY/+Oo+ZcBGanrQs5q8cMS6Npywpv5+Ws1gRlLtL6i 187Y1NYlVfoTZQsmzhJZ1URWq+bRFnVQdXvoF5gq8mCNtUEyQ7SAlIBAUHGKiKgLYhZR 3cfJx8TVJkKJPRv4+SbYBmN7Hwkq0RLbowjPcS93esbRfPMFZSko3xiQGY92GIUXlBMv IgIlv57/qnE6o/c+bRgHHWhNW9UCLcMEzQdA+om/h5XyfvW1oi/tdUpi+bOlNpUSDo7D YsDw== X-Gm-Message-State: APt69E3T+Q5Znzw7yczFoFuaNsTH0t/N8YhSxUpVgKFuvZhOHyj9Augj F+6W+XYmABHiQ8QAfgmhPPNzDaaihQCG/hoGpZTB1A== X-Google-Smtp-Source: ADUXVKImJrSlJGke9JWWBxKBaO//8NsX9y1sf41DQ3VWePELSr6dAE0LAJwKLp3DxxR874BKCMM0CuR3T5jx9w20jWo= X-Received: by 2002:a6b:6709:: with SMTP id b9-v6mr5427580ioc.170.1527758268101; Thu, 31 May 2018 02:17:48 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:bb86:0:0:0:0:0 with HTTP; Thu, 31 May 2018 02:17:47 -0700 (PDT) In-Reply-To: <20180531091120.u3oqbzskpr6rnhen@bivouac.eciton.net> References: <20180530181929.5066-1-ard.biesheuvel@linaro.org> <20180530181929.5066-2-ard.biesheuvel@linaro.org> <20180531091120.u3oqbzskpr6rnhen@bivouac.eciton.net> From: Ard Biesheuvel Date: Thu, 31 May 2018 11:17:47 +0200 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Masahisa Kojima Subject: Re: [PATCH edk2-platforms 1/3] Silicon/SynQuacerPciHostBridgeLib: add workaround for PCIe MMIO64 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 May 2018 09:17:49 -0000 Content-Type: text/plain; charset="UTF-8" On 31 May 2018 at 11:11, Leif Lindholm wrote: > On Wed, May 30, 2018 at 08:19:27PM +0200, Ard Biesheuvel wrote: >> From: Masahisa KOJIMA >> >> The current revision of SC2A11 contains PCIe bus issue. >> In MRd transaction, 1st/Last DW BE fields are not correctly set >> by hardware. >> >> As a workaround, set TH bit and specify MSG_CODE in iATU. >> With this setup, the value specified as MSG_CODE is set to the >> 1st/Last DW BE fields and PCIe controller can emit the correct >> MRd TLP header. >> Same workaround was already included for MMIO32 region, >> MMIO64 region also requires this workaround. >> Some deivices, such as Samsong SSD 970 EVO, do not work >> without this modification. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Masahisa KOJIMA > > Please add own S-o-b. > >> --- >> Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 5 +++-- >> 1 file changed, 3 insertions(+), 2 deletions(-) >> >> diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c >> index e4679543cc66..227f9a725ce8 100644 >> --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c >> +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c >> @@ -359,8 +359,9 @@ PciInitControllerPost ( >> RootBridge->MemAbove4G.Base, >> RootBridge->MemAbove4G.Base, >> RootBridge->MemAbove4G.Limit - RootBridge->MemAbove4G.Base + 1, >> - IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, >> - 0); >> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | >> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, >> + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); > > Hmm ... > This fix clearly needs to go in. But since this is working around a > bug in first-revision silicon, should we not have something > conditional here? > In theory, yes. In practice, we have no idea yet whether a fixed revision will ever materialize (the limited respin for the next revision does not address this issue afaik), nor do we have any idea how to distinguish them at runtime. Also, it is unlikely that we will need to run older firmware builds on these new chips. So for the time being, I think it is reasonable to apply this unconditionally (like we do for the MMIO32 region already)