* [PATCH] MdePkg/BaseIoLibIntrinsicArmVirt ARM: avoid double word loads and stores
@ 2018-11-07 13:13 Ard Biesheuvel
2018-11-07 13:38 ` Ard Biesheuvel
0 siblings, 1 reply; 6+ messages in thread
From: Ard Biesheuvel @ 2018-11-07 13:13 UTC (permalink / raw)
To: edk2-devel
Cc: lersek, liming.gao, michael.d.kinney, marc.zyngier, leif.lindholm,
Ard Biesheuvel
BaseIoLibIntrinsicArmVirt was created to prevent LTO from merging
accesses to MMIO regions, resulting in instructions with multiple
output registers that KVM on ARM cannot emulate (since the exception
syndrome information that KVM relies on can only describe a single
output register)
However, using double word loads on ARM amounts to the same thing,
and so code that relies on doing 64-bit MMIO to regions that are
emulated under KVM (such as the GICv3 TYPER register) will still
suffer from the original issue.
So replace ldrd and strd with equivalent two instruction sequences.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
index 3ad22bd5706d..0d802d6928d6 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
+++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
@@ -125,7 +125,8 @@ ASM_PFX(MmioWrite32Internal):
// @return The value read.
//
ASM_PFX(MmioRead64Internal):
- ldrd r0, r1, [r0]
+ ldr r1, [r0, #4]
+ ldr r0, [r0]
dmb
bx lr
@@ -141,5 +142,6 @@ ASM_PFX(MmioRead64Internal):
//
ASM_PFX(MmioWrite64Internal):
dmb st
- strd r2, r3, [r0]
+ str r2, [r0]
+ str r3, [r0, #4]
bx lr
--
2.19.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] MdePkg/BaseIoLibIntrinsicArmVirt ARM: avoid double word loads and stores
2018-11-07 13:13 [PATCH] MdePkg/BaseIoLibIntrinsicArmVirt ARM: avoid double word loads and stores Ard Biesheuvel
@ 2018-11-07 13:38 ` Ard Biesheuvel
2018-11-07 16:47 ` Philippe Mathieu-Daudé
2018-11-14 22:15 ` Leif Lindholm
0 siblings, 2 replies; 6+ messages in thread
From: Ard Biesheuvel @ 2018-11-07 13:38 UTC (permalink / raw)
To: edk2-devel@lists.01.org
Cc: Laszlo Ersek, Gao, Liming, Kinney, Michael D, Marc Zyngier,
Leif Lindholm, Ard Biesheuvel
On 7 November 2018 at 14:13, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> BaseIoLibIntrinsicArmVirt was created to prevent LTO from merging
> accesses to MMIO regions, resulting in instructions with multiple
> output registers that KVM on ARM cannot emulate (since the exception
> syndrome information that KVM relies on can only describe a single
> output register)
>
> However, using double word loads on ARM amounts to the same thing,
> and so code that relies on doing 64-bit MMIO to regions that are
> emulated under KVM (such as the GICv3 TYPER register) will still
> suffer from the original issue.
>
> So replace ldrd and strd with equivalent two instruction sequences.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Please consider this patch with the hunk below appended
> ---
> MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
> index 3ad22bd5706d..0d802d6928d6 100644
> --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
> +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
> @@ -125,7 +125,8 @@ ASM_PFX(MmioWrite32Internal):
> // @return The value read.
> //
> ASM_PFX(MmioRead64Internal):
> - ldrd r0, r1, [r0]
> + ldr r1, [r0, #4]
> + ldr r0, [r0]
> dmb
> bx lr
>
> @@ -141,5 +142,6 @@ ASM_PFX(MmioRead64Internal):
> //
> ASM_PFX(MmioWrite64Internal):
> dmb st
> - strd r2, r3, [r0]
> + str r2, [r0]
> + str r3, [r0, #4]
> bx lr
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
index e1a3d68a430c..deba8c1f0c59 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
+++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
@@ -127,7 +127,8 @@ MmioWrite32Internal
; @return The value read.
;
MmioRead64Internal
- ldrd r0, r1, [r0]
+ ldr r1, [r0, #4]
+ ldr r0, [r0]
dmb
bx lr
@@ -143,7 +144,8 @@ MmioRead64Internal
;
MmioWrite64Internal
dmb st
- strd r2, r3, [r0]
+ str r2, [r0]
+ str r3, [r0, #4]
bx lr
END
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] MdePkg/BaseIoLibIntrinsicArmVirt ARM: avoid double word loads and stores
2018-11-07 13:38 ` Ard Biesheuvel
@ 2018-11-07 16:47 ` Philippe Mathieu-Daudé
2018-11-07 19:30 ` Laszlo Ersek
2018-11-14 22:15 ` Leif Lindholm
1 sibling, 1 reply; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-11-07 16:47 UTC (permalink / raw)
To: Ard Biesheuvel, edk2-devel@lists.01.org
Cc: Marc Zyngier, Gao, Liming, Kinney, Michael D, Laszlo Ersek
On 7/11/18 14:38, Ard Biesheuvel wrote:
> On 7 November 2018 at 14:13, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
>> BaseIoLibIntrinsicArmVirt was created to prevent LTO from merging
>> accesses to MMIO regions, resulting in instructions with multiple
>> output registers that KVM on ARM cannot emulate (since the exception
>> syndrome information that KVM relies on can only describe a single
>> output register)
>>
>> However, using double word loads on ARM amounts to the same thing,
>> and so code that relies on doing 64-bit MMIO to regions that are
>> emulated under KVM (such as the GICv3 TYPER register) will still
>> suffer from the original issue.
>>
>> So replace ldrd and strd with equivalent two instruction sequences.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>
> Please consider this patch with the hunk below appended
>
>> ---
>> MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S | 6 ++++--
>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
>> index 3ad22bd5706d..0d802d6928d6 100644
>> --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
>> +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
>> @@ -125,7 +125,8 @@ ASM_PFX(MmioWrite32Internal):
>> // @return The value read.
>> //
>> ASM_PFX(MmioRead64Internal):
>> - ldrd r0, r1, [r0]
>> + ldr r1, [r0, #4]
>> + ldr r0, [r0]
Ard remembered me UEFI is little-endian only :)
Thus this code is safe.
With the hunk appended:
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> dmb
>> bx lr
>>
>> @@ -141,5 +142,6 @@ ASM_PFX(MmioRead64Internal):
>> //
>> ASM_PFX(MmioWrite64Internal):
>> dmb st
>> - strd r2, r3, [r0]
>> + str r2, [r0]
>> + str r3, [r0, #4]
>> bx lr
>
> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> index e1a3d68a430c..deba8c1f0c59 100644
> --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> @@ -127,7 +127,8 @@ MmioWrite32Internal
> ; @return The value read.
> ;
> MmioRead64Internal
> - ldrd r0, r1, [r0]
> + ldr r1, [r0, #4]
> + ldr r0, [r0]
> dmb
> bx lr
>
> @@ -143,7 +144,8 @@ MmioRead64Internal
> ;
> MmioWrite64Internal
> dmb st
> - strd r2, r3, [r0]
> + str r2, [r0]
> + str r3, [r0, #4]
> bx lr
>
> END
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] MdePkg/BaseIoLibIntrinsicArmVirt ARM: avoid double word loads and stores
2018-11-07 16:47 ` Philippe Mathieu-Daudé
@ 2018-11-07 19:30 ` Laszlo Ersek
0 siblings, 0 replies; 6+ messages in thread
From: Laszlo Ersek @ 2018-11-07 19:30 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Ard Biesheuvel,
edk2-devel@lists.01.org
Cc: Marc Zyngier, Gao, Liming, Kinney, Michael D
On 11/07/18 17:47, Philippe Mathieu-Daudé wrote:
> On 7/11/18 14:38, Ard Biesheuvel wrote:
>> On 7 November 2018 at 14:13, Ard Biesheuvel
>> <ard.biesheuvel@linaro.org> wrote:
>>> BaseIoLibIntrinsicArmVirt was created to prevent LTO from merging
>>> accesses to MMIO regions, resulting in instructions with multiple
>>> output registers that KVM on ARM cannot emulate (since the exception
>>> syndrome information that KVM relies on can only describe a single
>>> output register)
>>>
>>> However, using double word loads on ARM amounts to the same thing,
>>> and so code that relies on doing 64-bit MMIO to regions that are
>>> emulated under KVM (such as the GICv3 TYPER register) will still
>>> suffer from the original issue.
>>>
>>> So replace ldrd and strd with equivalent two instruction sequences.
>>>
>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>>
>> Please consider this patch with the hunk below appended
>>
>>> ---
>>> MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S | 6 ++++--
>>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
>>> b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
>>> index 3ad22bd5706d..0d802d6928d6 100644
>>> --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
>>> +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
>>> @@ -125,7 +125,8 @@ ASM_PFX(MmioWrite32Internal):
>>> // @return The value read.
>>> //
>>> ASM_PFX(MmioRead64Internal):
>>> - ldrd r0, r1, [r0]
>>> + ldr r1, [r0, #4]
>>> + ldr r0, [r0]
>
> Ard remembered me UEFI is little-endian only :)
> Thus this code is safe.
>
> With the hunk appended:
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
So, this is for 32-bit ARM only, IIUC. (Supported also by the pathnames
of the files being modified.)
The commit message makes sense, and the patch looks plausible. (I didn't
go to the ARM ARM to verify the syntax, and I admit I don't know the
syntax without looking it up.)
Acked-by: Laszlo Ersek <lersek@redhat.com>
Thanks!
Laszlo
>
>>> dmb
>>> bx lr
>>>
>>> @@ -141,5 +142,6 @@ ASM_PFX(MmioRead64Internal):
>>> //
>>> ASM_PFX(MmioWrite64Internal):
>>> dmb st
>>> - strd r2, r3, [r0]
>>> + str r2, [r0]
>>> + str r3, [r0, #4]
>>> bx lr
>>
>> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
>> b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
>> index e1a3d68a430c..deba8c1f0c59 100644
>> --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
>> +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
>> @@ -127,7 +127,8 @@ MmioWrite32Internal
>> ; @return The value read.
>> ;
>> MmioRead64Internal
>> - ldrd r0, r1, [r0]
>> + ldr r1, [r0, #4]
>> + ldr r0, [r0]
>> dmb
>> bx lr
>>
>> @@ -143,7 +144,8 @@ MmioRead64Internal
>> ;
>> MmioWrite64Internal
>> dmb st
>> - strd r2, r3, [r0]
>> + str r2, [r0]
>> + str r3, [r0, #4]
>> bx lr
>>
>> END
>> _______________________________________________
>> edk2-devel mailing list
>> edk2-devel@lists.01.org
>> https://lists.01.org/mailman/listinfo/edk2-devel
>>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] MdePkg/BaseIoLibIntrinsicArmVirt ARM: avoid double word loads and stores
2018-11-07 13:38 ` Ard Biesheuvel
2018-11-07 16:47 ` Philippe Mathieu-Daudé
@ 2018-11-14 22:15 ` Leif Lindholm
2018-11-15 13:08 ` Ard Biesheuvel
1 sibling, 1 reply; 6+ messages in thread
From: Leif Lindholm @ 2018-11-14 22:15 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel@lists.01.org, Laszlo Ersek, Gao, Liming,
Kinney, Michael D, Marc Zyngier
On Wed, Nov 07, 2018 at 02:38:37PM +0100, Ard Biesheuvel wrote:
> On 7 November 2018 at 14:13, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> > BaseIoLibIntrinsicArmVirt was created to prevent LTO from merging
> > accesses to MMIO regions, resulting in instructions with multiple
> > output registers that KVM on ARM cannot emulate (since the exception
> > syndrome information that KVM relies on can only describe a single
> > output register)
> >
> > However, using double word loads on ARM amounts to the same thing,
> > and so code that relies on doing 64-bit MMIO to regions that are
> > emulated under KVM (such as the GICv3 TYPER register) will still
> > suffer from the original issue.
> >
> > So replace ldrd and strd with equivalent two instruction sequences.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>
> Please consider this patch with the hunk below appended
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> > ---
> > MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S | 6 ++++--
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
> > index 3ad22bd5706d..0d802d6928d6 100644
> > --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
> > +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
> > @@ -125,7 +125,8 @@ ASM_PFX(MmioWrite32Internal):
> > // @return The value read.
> > //
> > ASM_PFX(MmioRead64Internal):
> > - ldrd r0, r1, [r0]
> > + ldr r1, [r0, #4]
> > + ldr r0, [r0]
> > dmb
> > bx lr
> >
> > @@ -141,5 +142,6 @@ ASM_PFX(MmioRead64Internal):
> > //
> > ASM_PFX(MmioWrite64Internal):
> > dmb st
> > - strd r2, r3, [r0]
> > + str r2, [r0]
> > + str r3, [r0, #4]
> > bx lr
>
> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> index e1a3d68a430c..deba8c1f0c59 100644
> --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> @@ -127,7 +127,8 @@ MmioWrite32Internal
> ; @return The value read.
> ;
> MmioRead64Internal
> - ldrd r0, r1, [r0]
> + ldr r1, [r0, #4]
> + ldr r0, [r0]
> dmb
> bx lr
>
> @@ -143,7 +144,8 @@ MmioRead64Internal
> ;
> MmioWrite64Internal
> dmb st
> - strd r2, r3, [r0]
> + str r2, [r0]
> + str r3, [r0, #4]
> bx lr
>
> END
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] MdePkg/BaseIoLibIntrinsicArmVirt ARM: avoid double word loads and stores
2018-11-14 22:15 ` Leif Lindholm
@ 2018-11-15 13:08 ` Ard Biesheuvel
0 siblings, 0 replies; 6+ messages in thread
From: Ard Biesheuvel @ 2018-11-15 13:08 UTC (permalink / raw)
To: Leif Lindholm
Cc: edk2-devel@lists.01.org, Laszlo Ersek, Gao, Liming,
Kinney, Michael D, Marc Zyngier
On Wed, 14 Nov 2018 at 14:15, Leif Lindholm <leif.lindholm@linaro.org> wrote:
>
> On Wed, Nov 07, 2018 at 02:38:37PM +0100, Ard Biesheuvel wrote:
> > On 7 November 2018 at 14:13, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> > > BaseIoLibIntrinsicArmVirt was created to prevent LTO from merging
> > > accesses to MMIO regions, resulting in instructions with multiple
> > > output registers that KVM on ARM cannot emulate (since the exception
> > > syndrome information that KVM relies on can only describe a single
> > > output register)
> > >
> > > However, using double word loads on ARM amounts to the same thing,
> > > and so code that relies on doing 64-bit MMIO to regions that are
> > > emulated under KVM (such as the GICv3 TYPER register) will still
> > > suffer from the original issue.
> > >
> > > So replace ldrd and strd with equivalent two instruction sequences.
> > >
> > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >
> > Please consider this patch with the hunk below appended
>
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
>
Pushed as 9cabe9d45755fa4e7412e4eba7825d0c46982001
> > > ---
> > > MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S | 6 ++++--
> > > 1 file changed, 4 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
> > > index 3ad22bd5706d..0d802d6928d6 100644
> > > --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
> > > +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S
> > > @@ -125,7 +125,8 @@ ASM_PFX(MmioWrite32Internal):
> > > // @return The value read.
> > > //
> > > ASM_PFX(MmioRead64Internal):
> > > - ldrd r0, r1, [r0]
> > > + ldr r1, [r0, #4]
> > > + ldr r0, [r0]
> > > dmb
> > > bx lr
> > >
> > > @@ -141,5 +142,6 @@ ASM_PFX(MmioRead64Internal):
> > > //
> > > ASM_PFX(MmioWrite64Internal):
> > > dmb st
> > > - strd r2, r3, [r0]
> > > + str r2, [r0]
> > > + str r3, [r0, #4]
> > > bx lr
> >
> > diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> > b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> > index e1a3d68a430c..deba8c1f0c59 100644
> > --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> > +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
> > @@ -127,7 +127,8 @@ MmioWrite32Internal
> > ; @return The value read.
> > ;
> > MmioRead64Internal
> > - ldrd r0, r1, [r0]
> > + ldr r1, [r0, #4]
> > + ldr r0, [r0]
> > dmb
> > bx lr
> >
> > @@ -143,7 +144,8 @@ MmioRead64Internal
> > ;
> > MmioWrite64Internal
> > dmb st
> > - strd r2, r3, [r0]
> > + str r2, [r0]
> > + str r3, [r0, #4]
> > bx lr
> >
> > END
^ permalink raw reply [flat|nested] 6+ messages in thread
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2018-11-07 13:13 [PATCH] MdePkg/BaseIoLibIntrinsicArmVirt ARM: avoid double word loads and stores Ard Biesheuvel
2018-11-07 13:38 ` Ard Biesheuvel
2018-11-07 16:47 ` Philippe Mathieu-Daudé
2018-11-07 19:30 ` Laszlo Ersek
2018-11-14 22:15 ` Leif Lindholm
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