From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::141; helo=mail-it1-x141.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it1-x141.google.com (mail-it1-x141.google.com [IPv6:2607:f8b0:4864:20::141]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 39C972118C51F for ; Wed, 7 Nov 2018 05:38:38 -0800 (PST) Received: by mail-it1-x141.google.com with SMTP id p11-v6so13102050itf.0 for ; Wed, 07 Nov 2018 05:38:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=BfPGP4KBQfzN6NqA4WiyaeX0Q7goLtp8shmDvOCUmsc=; b=NIcBCcoVxD8j5sGN0XQpM8oB9Q/rpixk/vTfZfwNU/VfTn6cs0WKUTOHcEbH0SpFkS nMtrIKOAmAnc8IPqvCi9LppdoGBQjUT+xrZUWv2r8N11vt+53alKI8Yjq/ksQzuiEA11 BeAShsjxgms4kqc2do1WhMmgNYXeAJnXJsb7E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=BfPGP4KBQfzN6NqA4WiyaeX0Q7goLtp8shmDvOCUmsc=; b=qTk7SrfaoUoJMPHutQIWPLuQQdJJOwfs8bx9ZEMYLpCxn5dDrMzJHRb4dQG8AU4E6f E0RRRFBIWkfSg/NmdLHTTSFuToi/y0pwX6g/dR5Ln+DxQ7UMhrn8xkmnkcCVzdxfhfeD VpMehnlvhXArod2Yxt9r4P2wdSXNS29oWSdWpCY3O/gaT79cBHo5eOczZFrpXNmiZ08m OHoN+7J2s9Bx5MwRvfG4eBrG2bkBUhwIxlTDJpEGllWqNQ/qbo8LK4VDFTw1/gXJlExY 9/3feaUkj6qZ0GJCdijwFuQEV6wyguiCF7J5nOols1U67p9jNAwGzSIBFw8xy5J/pCOM GFnw== X-Gm-Message-State: AGRZ1gKKuPTwC8xFuqK/rpG9CkHiVRAoOyVx6kwxiOyvqORSaprjUwWz Wasd/lLInqrBTbpGHpLWFuCqa86WG2JAyjUsYwuGW22uot0= X-Google-Smtp-Source: AJdET5c/9TZqXih0H3+ogQhXS0N8mbEBhvOvH90nN0htPB+8R0DCQpJP+uelM87lbp7RecB6/MXGe1dzFUV8BrcmUEM= X-Received: by 2002:a24:7d8d:: with SMTP id b135-v6mr172769itc.121.1541597917650; Wed, 07 Nov 2018 05:38:37 -0800 (PST) MIME-Version: 1.0 Received: by 2002:a6b:4f16:0:0:0:0:0 with HTTP; Wed, 7 Nov 2018 05:38:37 -0800 (PST) In-Reply-To: <20181107131301.15852-1-ard.biesheuvel@linaro.org> References: <20181107131301.15852-1-ard.biesheuvel@linaro.org> From: Ard Biesheuvel Date: Wed, 7 Nov 2018 14:38:37 +0100 Message-ID: To: "edk2-devel@lists.01.org" Cc: Laszlo Ersek , "Gao, Liming" , "Kinney, Michael D" , Marc Zyngier , Leif Lindholm , Ard Biesheuvel Subject: Re: [PATCH] MdePkg/BaseIoLibIntrinsicArmVirt ARM: avoid double word loads and stores X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Nov 2018 13:38:39 -0000 Content-Type: text/plain; charset="UTF-8" On 7 November 2018 at 14:13, Ard Biesheuvel wrote: > BaseIoLibIntrinsicArmVirt was created to prevent LTO from merging > accesses to MMIO regions, resulting in instructions with multiple > output registers that KVM on ARM cannot emulate (since the exception > syndrome information that KVM relies on can only describe a single > output register) > > However, using double word loads on ARM amounts to the same thing, > and so code that relies on doing 64-bit MMIO to regions that are > emulated under KVM (such as the GICv3 TYPER register) will still > suffer from the original issue. > > So replace ldrd and strd with equivalent two instruction sequences. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Please consider this patch with the hunk below appended > --- > MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S > index 3ad22bd5706d..0d802d6928d6 100644 > --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S > +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S > @@ -125,7 +125,8 @@ ASM_PFX(MmioWrite32Internal): > // @return The value read. > // > ASM_PFX(MmioRead64Internal): > - ldrd r0, r1, [r0] > + ldr r1, [r0, #4] > + ldr r0, [r0] > dmb > bx lr > > @@ -141,5 +142,6 @@ ASM_PFX(MmioRead64Internal): > // > ASM_PFX(MmioWrite64Internal): > dmb st > - strd r2, r3, [r0] > + str r2, [r0] > + str r3, [r0, #4] > bx lr diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm index e1a3d68a430c..deba8c1f0c59 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm @@ -127,7 +127,8 @@ MmioWrite32Internal ; @return The value read. ; MmioRead64Internal - ldrd r0, r1, [r0] + ldr r1, [r0, #4] + ldr r0, [r0] dmb bx lr @@ -143,7 +144,8 @@ MmioRead64Internal ; MmioWrite64Internal dmb st - strd r2, r3, [r0] + str r2, [r0] + str r3, [r0, #4] bx lr END