From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::244; helo=mail-it0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x244.google.com (mail-it0-x244.google.com [IPv6:2607:f8b0:4001:c0b::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 55ED2209574CB for ; Tue, 27 Feb 2018 09:39:05 -0800 (PST) Received: by mail-it0-x244.google.com with SMTP id k135so173852ite.2 for ; Tue, 27 Feb 2018 09:45:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=ycnDfWQ+uFA02mxMEUqlNfhuHRiPUXLU+mHW6S5zi8Q=; b=RaRRKweU7378vxlc1j/XzjWWX570DsopgwPpDccbyFNKaiHiHEyMDFhT1LlKn5cW8f 7v6KsKQtSpoPCBQBz2P+BZZREyGaU0CnZfgta+ohXlNzaRv3bHB0I8Z4FosEwwEUel4r +BAbAn+SyPffijfnHByhs+MYN4RxX1go+J1bE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=ycnDfWQ+uFA02mxMEUqlNfhuHRiPUXLU+mHW6S5zi8Q=; b=Lk4uGxKityMdqtpQdsUvYfkzlC3drJnctp5QtV8GdyO5sd0bQBgi5b2XvEjUCPWusR I8Nd3vqwk3dBx+KkHnMqjWr2AkOxZxsMhPu4ZoFIBb11mEj4IIH/vJl3lrbXxOqCPaSe Ui5EDR9MspmTdMJdqVlDNQa976ijo8jNIGqWdztkI6HkhLsaRZF849eetJR9wmCZe3yL qVccuGosgKwQKMEmAYgI7vZwGYvX1vzCloJis5qvD+oLj04/YGXitf3SEo6Um0ytjyEN bs0W2ttNoSM2XU4lfqSD/IlktzjkWIEY/G0leN8GNPQ2b8kN3ao5/zXSzCRRKvyixkPf yp8Q== X-Gm-Message-State: APf1xPAea7LvLC8i635Q851+YevFLxsW1TeuMOntDtNGGiYnAbka3pT/ dcJJT6+PATZJp/Rk/dAjVSh8rtnq9HDGm68kvUVphA== X-Google-Smtp-Source: AH8x224z071CwjDVC/c3YTI6WUJyYG/NqAamunurY03p6ZNM6FHDSgk/fixoh3DURLeZrVgLwZG1fn9Oi7MKT+tWkpo= X-Received: by 10.36.91.138 with SMTP id g132mr17644485itb.50.1519753510980; Tue, 27 Feb 2018 09:45:10 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.138.209 with HTTP; Tue, 27 Feb 2018 09:45:09 -0800 (PST) In-Reply-To: <20180227173640.vavijseacrm5wnau@bivouac.eciton.net> References: <20180227134747.13238-1-ard.biesheuvel@linaro.org> <20180227173640.vavijseacrm5wnau@bivouac.eciton.net> From: Ard Biesheuvel Date: Tue, 27 Feb 2018 17:45:09 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacer: add stage 2 override translation tables for PCIe X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Feb 2018 17:39:05 -0000 Content-Type: text/plain; charset="UTF-8" On 27 February 2018 at 17:36, Leif Lindholm wrote: > > On Tue, Feb 27, 2018 at 05:19:59PM +0000, Ard Biesheuvel wrote: >> On 27 February 2018 at 13:47, Ard Biesheuvel wrote: >> > The Designware PCIe IP in the SynQuacer SoC needs a little help to >> > appear sane to the OS. Not only does it lack a true root port, and >> > therefore does not perform any filtering whatsoever of type 0 config >> > TLPs that are not intended for the link peer, it also has trouble >> > issuing 64-bit wide MMIO accesses, which are often used on MMIO BARs >> > with memory semantics (e.g., frame buffers). >> > >> > So let's create a stage 2 mapping covering the entire physical address >> > space, and remap some ECAM regions and demote write combine attributes >> > to device/strongly ordered. This is not a water tight fix, but it does >> > work around the issues in the majority of cases. >> > >> > (Note that the ECAM remapping can also be addressed in the SMMU mapping >> > of the PCIe IP exposed to the CPU, but this is currently under >> > development, and it does not hurt to have it in two places) >> > >> > Contributed-under: TianoCore Contribution Agreement 1.1 >> > Signed-off-by: Ard Biesheuvel >> > --- >> > This is a followup to/replacement for '[RFC PATCH edk2-non-osi] >> > Platform/DeveloperBox: add prebuilt binary containing stage 2 page tables' >> > >> > Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 1 + >> > Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 5 +- >> > Silicon/Socionext/SynQuacer/Stage2Tables/GNUmakefile | 23 +++++ >> > Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 88 ++++++++++++++++++++ >> > Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.inf | 32 +++++++ >> > 5 files changed, 148 insertions(+), 1 deletion(-) >> > >> ... >> > diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.inf b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.inf >> > new file mode 100644 >> > index 000000000000..9bec659af444 >> > --- /dev/null >> > +++ b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.inf >> > @@ -0,0 +1,32 @@ >> > +## @file >> > +# >> > +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
>> > +# >> > +# This program and the accompanying materials >> > +# are licensed and made available under the terms and conditions of the BSD License >> > +# which accompanies this distribution. The full text of the license may be found at >> > +# http://opensource.org/licenses/bsd-license.php >> > +# >> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. >> > +# >> > +## >> > + >> > +[Defines] >> > + INF_VERSION = 0x0001001A >> > + BASE_NAME = Stage2Tables >> > + FILE_GUID = e11cbca5-8f82-41a7-8441-02b48acc13a7 >> > + MODULE_TYPE = USER_DEFINED >> > + VERSION_STRING = 1.0 >> > + CUSTOM_MAKEFILE = GCC|GNUmakefile >> > + >> > +[Sources] >> > + Stage2Tables.S >> > + >> > +[Packages] >> > + MdePkg/MdePkg.dec >> > + Silicon/Socionext/SynQuacer/SynQuacer.dec >> > + >> > +[BuildOptions] >> > + *_*_*_OBJCOPY_PATH == objcopy >> > + *_*_*_OBJCOPY_FLAGS == -I elf64-little -O binary -j .rodata >> >> I can improve this and fix Clang at the same time by adding >> >> *_*_*_ASM_FLAGS == -nostdlib >> -Wl,-e,0x81f8000,--section-start=.rodata=0x81f8000 >> *_CLANG35_*_ASM_FLAGS = -no-integrated-as >> *_CLANG38_*_ASM_FLAGS = -no-integrated-as >> >> (and remove the linker arguments from the Makefile) > > I can confirm this resolves the CLANG issue. > > Could we do this with a CLANG_ALL_ASM_FLAGS, rather than listing each > new toolchain profile as they get added? > No, not really. CLANG3x is not a separate toolchain family, so we can apply things to GCC+CLANG combined, or to certain versions individually.