From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::241; helo=mail-it0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x241.google.com (mail-it0-x241.google.com [IPv6:2607:f8b0:4001:c0b::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 19DD9222DDBF6 for ; Mon, 15 Jan 2018 03:59:15 -0800 (PST) Received: by mail-it0-x241.google.com with SMTP id b77so629851itd.0 for ; Mon, 15 Jan 2018 04:04:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=r8/3RH9pumDzBIef0O+S4/BW8z/kDVRZ8lf5zPV4DL8=; b=YeK8rN4hxDeR6bAyAZsPbw08iPIhMytuTLRayqfb/I7ubI0uuWE481RqGX9TPhaomG bdS9y+COo6SAr83Ita7av+vpzuDWM33xgCx5Y3com10r45/Suw83+W04L/TAvUnjWt0P UHWqueUJIxByjUzNewAAWBsPRw/vAg1/n2Fwk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=r8/3RH9pumDzBIef0O+S4/BW8z/kDVRZ8lf5zPV4DL8=; b=qap8uZfl4YxSsY83tMPMgGmMxHBYtPnP5ePPXHf0zq270edClUyPFrY0z0CNWykYJE TictPOHgMOOVlaosSGfNIMrRJpUSHVtMJp+hW7KJqOY1tpBPAm9A+ybKWK5DnH5g65X4 boct1Ujb99omJZ8wt6KcUXPoVBIaF/9pzSUgYctn0qg5t8+YiumkLVzOp22H5tmZBLUv SYwE39G68YA+SjZ6+ryRUndcAot19PEAQeMFlmPS/lHDqrQRbAsDRW1LOTk76WV6Sgla xj1CHNcrOqF34yIbeKceiWoNDTK9hkGpkdBSoKzvxn3wfdcPRZzz/KN9ccKwLJB7yEyh 6zDA== X-Gm-Message-State: AKwxyteBtIoroAh+wo/h6abojt2VMITAIlJnXoW/dyAEj3jgNvqQHR3n N7Q1nSDywQrQJEpCuEoi8vWlw5JMDsmvy2KAREr5kA== X-Google-Smtp-Source: ACJfBosNEsL5Z6e4u0W/YsZ+Mj6MRpomVv0JJR7xNzQQdHj7r5cUp5abL96hIQlQPpUxqKIqkWHLVpYy6KuCf0d3bAE= X-Received: by 10.36.184.3 with SMTP id m3mr13630034ite.65.1516017872827; Mon, 15 Jan 2018 04:04:32 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.37.197 with HTTP; Mon, 15 Jan 2018 04:04:31 -0800 (PST) In-Reply-To: <20180113065245.10711-1-sigmaepsilon92@gmail.com> References: <20180113065245.10711-1-sigmaepsilon92@gmail.com> From: Ard Biesheuvel Date: Mon, 15 Jan 2018 12:04:31 +0000 Message-ID: To: Michael Zimmermann Cc: "edk2-devel@lists.01.org" , Leif Lindholm Subject: Re: [PATCH v2] ArmPkg/Library/ArmLib: add ArmWriteSctlr X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 15 Jan 2018 11:59:16 -0000 Content-Type: text/plain; charset="UTF-8" On 13 January 2018 at 06:52, Michael Zimmermann wrote: > This currently isn't needed by anything in the edk2 tree but > it's useful for externally maintained platforms which have > to set this register e.g. to disable alignment aborts. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Michael Zimmermann Reviewed-by: Ard Biesheuvel Pushed as 1e1d16971d1a Thanks! > --- > ArmPkg/Include/Library/ArmLib.h | 6 ++++++ > ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 9 +++++++++ > ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 4 ++++ > ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm | 3 +++ > 4 files changed, 22 insertions(+) > > diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h > index 24e84c7a1965..ffda50e9d767 100644 > --- a/ArmPkg/Include/Library/ArmLib.h > +++ b/ArmPkg/Include/Library/ArmLib.h > @@ -558,6 +558,12 @@ ArmReadSctlr ( > VOID > ); > > +VOID > +EFIAPI > +ArmWriteSctlr ( > + IN UINT32 Value > + ); > + > UINTN > EFIAPI > ArmReadHVBar ( > diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > index 9d3dd66b10eb..1ef2f61f5979 100644 > --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > @@ -187,4 +187,13 @@ ASM_FUNC(ArmReadSctlr) > 3:mrs x0, sctlr_el3 > 4:ret > > +ASM_FUNC(ArmWriteSctlr) > + EL1_OR_EL2_OR_EL3(x1) > +1:msr sctlr_el1, x0 > + ret > +2:msr sctlr_el2, x0 > + ret > +3:msr sctlr_el3, x0 > +4:ret > + > ASM_FUNCTION_REMOVE_IF_UNREFERENCED > diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > index a0b5ed500298..149b57e059ee 100644 > --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > @@ -153,6 +153,10 @@ ASM_FUNC(ArmReadSctlr) > mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) > bx lr > > +ASM_FUNC(ArmWriteSctlr) > + mcr p15, 0, r0, c1, c0, 0 > + bx lr > + > ASM_FUNC(ArmReadCpuActlr) > mrc p15, 0, r0, c1, c0, 1 > bx lr > diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm > index 85b0feee20d4..219140c22b13 100644 > --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm > +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm > @@ -155,6 +155,9 @@ > mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data) > bx lr > > + RVCT_ASM_EXPORT ArmWriteSctlr > + mcr p15, 0, r0, c1, c0, 0 > + bx lr > > RVCT_ASM_EXPORT ArmReadCpuActlr > mrc p15, 0, r0, c1, c0, 1 > -- > 2.15.1 >