From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-it0-x236.google.com (mail-it0-x236.google.com [IPv6:2607:f8b0:4001:c0b::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 67E272041D9E0 for ; Wed, 29 Mar 2017 07:22:37 -0700 (PDT) Received: by mail-it0-x236.google.com with SMTP id 190so57140275itm.0 for ; Wed, 29 Mar 2017 07:22:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=ZJ4Qf51QqPj6YPsX3kordm0K7b1hvZJ1fnkOEc3B59I=; b=KT9MAYWIA6CeJUbAXg97pFyJiiYVpLj+nvcxcm2OWBs/oyJmIfiGlfhHUlYzhEkGHY sN3sdQi/4gqkmWzsgqMHTMPvLbjb7JLz3f7a8oHyNE4T2FNU1jdD2F2hEKC9lKyDoWHX B8m6WVwSZfprL/6Gs6fuu78AMYDn7HOIwQnpM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=ZJ4Qf51QqPj6YPsX3kordm0K7b1hvZJ1fnkOEc3B59I=; b=m2B/XLrh6cLSmCHkB7J8lFtYzYiSkWirGUqc76uoxzQAfLXpQKrBCALSU0Iiu8VONA RVBBhPiCEE9mW3oTNL+TfH56YVXTH6rbqiapKJh86dcUJR1xL36jWKWI9L7JruxuLtYD 19CB8v8SyzFoNr/RGbWLXj/pNs4qyfnztAxNj32rzOrmYb3srmSjvYCfrbDsIiVVyOgJ yloIdLPA9u6DPVfJGkDOptDtLh78i+dOyaWerZ5+z/Dy05ALrphvhcOYSs9v8Hh+WHuS +0/DZP+D4DnfhekZe+mUJaFPVvWP0+qelHsl3GreevrksTDk4aAF+WxQYAdB/0s9ck4K mIRA== X-Gm-Message-State: AFeK/H36rmK9kfigCB4vjfuuHrC703Azwtf4UpDoKzso8KWNCyxzGPR22F78crupu6l6b/+I7yVjUCoPKbl2j1Nk X-Received: by 10.36.137.4 with SMTP id s4mr1379250itd.63.1490797355789; Wed, 29 Mar 2017 07:22:35 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.10.27 with HTTP; Wed, 29 Mar 2017 07:22:35 -0700 (PDT) In-Reply-To: <74D8A39837DF1E4DA445A8C0B3885C503A916565@shsmsx102.ccr.corp.intel.com> References: <1490434122-16200-1-git-send-email-jiewen.yao@intel.com> <1490434122-16200-2-git-send-email-jiewen.yao@intel.com> <74D8A39837DF1E4DA445A8C0B3885C503A916565@shsmsx102.ccr.corp.intel.com> From: Ard Biesheuvel Date: Wed, 29 Mar 2017 15:22:35 +0100 Message-ID: To: "Yao, Jiewen" Cc: "Kinney, Michael D" , "Ni, Ruiyu" , Leo Duran , "edk2-devel@lists.01.org" , Brijesh Singh Subject: Re: [PATCH 1/3] MdeModulePkg/Include: Add IOMMU protocol definition. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Mar 2017 14:22:37 -0000 Content-Type: text/plain; charset=UTF-8 On 29 March 2017 at 00:45, Yao, Jiewen wrote: > Agree. That is a good idea. > > > > I will add that in V2 patch. > Hello Jiewen, As a bit of background, what I have in mind is an enhancement of the PCI root bridge I/O allocate, map and unmap methods so that situations that would currently lead to failure or to suboptimal performance are left for the IOMMU protocol to handle if one is present. Note that this may imply having IOMMU protocol instances for each PCI root bridge, and for other masters as well. (For example, AMD Seattle has separate IOMMUs for PCI and for the networking controllers, which are wired to the internal interconnect directly) So in RootBridgeIoMap(), for instance, we have this condition PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress; if ((!RootBridge->DmaAbove4G || (Operation != EfiPciOperationBusMasterRead64 && Operation != EfiPciOperationBusMasterWrite64 && Operation != EfiPciOperationBusMasterCommonBuffer64)) && ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB)) { to decide whether bounce buffering is necessary (or even possible). The mapping between DeviceAddress and HostAddress could be supplied by the IOMMU protocol instance, which also means we should reinterpret DmaAbove4G and other variables related to 32-bit addressing to apply to the device address and not the physical address. Similarly, in RootBridgeIoAllocateBuffer(), a failure to allocate below 4 GB may not be an error if the IOMMU protocol instance can provide a 32-bit addressable mapping for it. I am aware that this complicates matters for you, but having IOMMU support in the generic PCI host bridge driver is extremely useful for us. I am happy to help out in any way I can. Thanks, Ard.