From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=aGfaLVxi; spf=pass (domain: linaro.org, ip: 209.85.166.195, mailfrom: ard.biesheuvel@linaro.org) Received: from mail-it1-f195.google.com (mail-it1-f195.google.com [209.85.166.195]) by groups.io with SMTP; Fri, 24 May 2019 08:25:26 -0700 Received: by mail-it1-f195.google.com with SMTP id e184so14411141ite.1 for ; Fri, 24 May 2019 08:25:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=S1ydCTNvjq2IMuhBs40Lla3U5eg1u5p57JR95Z4FxWw=; b=aGfaLVxiwQbEsqTVfPSN4AbGucvpuNJe85qzI4AjHjFD+SGkTB07eKMkmIpIpYZOjQ ioz+lTUU8Bw2yz6Cge4jKRhT9OQds2a2epkE1ZBaWszvXGHJmF4/q5qxqXeUsiIM6SUc 3v8V/pVmPd4QV5BeO5dA/7YPtMNOR5qury0ChblGDywJKYqAqnHpYd3bQPVLzdNDu5BC fV3KNBqFq5i/4/nGeTVVt5wOXvITfY/DJal1uZVzFrLpFWZtppC3x2Tm0Az0H8lYQjoA WAwyl9k1EqfRr6OvWi7mG+xxcEJWfc9+GxjSqxRvteoCptNl5BKZNhxED2sirGbMWh1d hhgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=S1ydCTNvjq2IMuhBs40Lla3U5eg1u5p57JR95Z4FxWw=; b=GShvKSTBT2JhsZMt75nOVbHbVjoOxGfaVsFz6JgtlC2PAPZb/OIeunCEbiUjvb3wmC 6/nAZJj0VxlHv6+nv1ixfWNGxDhm73w/5kUO+oqUoIZ7wGEZ3D2qh4a+Ix69fktlhP5N 40t6NgyqmpT7+3FsNjyhwA82lFFszVi7cG5vg9LXGefeIg5gzFiJb/TtAbtNg5laxjEv sOszcZgUzITLPV2RnPgQ1auWHMHICnxcoN3HVEQUJFVXyaIsz1GUTkRJhk/48DUNCyYT E2cess3yeGzI/Pi0i9oqVj3kc+ZbDAK4eEaZifX1JAqFE2Lmjxenxpj5cI5Z7gvjcCqZ Ursg== X-Gm-Message-State: APjAAAX1GJX19joIzjB80+NLceSMsNSXMk6VvC5mM0JkD/X4+975mJ0p go/moOMgrcxLRgLlCSen0KaBMTpyFAqdT2c3GF0qrg== X-Google-Smtp-Source: APXvYqxa/yAXB0XOyWVNTOL4thFlS7T/g9mKgaXHPwwPIkms5G67fQWj9FV9sr/Itd7Ll7SxIAcutrmmRcVxyrXFpG4= X-Received: by 2002:a24:910b:: with SMTP id i11mr19734874ite.76.1558711526029; Fri, 24 May 2019 08:25:26 -0700 (PDT) MIME-Version: 1.0 References: <1558366047-15994-1-git-send-email-mw@semihalf.com> <1558366047-15994-7-git-send-email-mw@semihalf.com> In-Reply-To: From: "Ard Biesheuvel" Date: Fri, 24 May 2019 17:25:14 +0200 Message-ID: Subject: Re: [edk2-platforms: PATCH v2 06/14] Marvell/Armada7k8k: Add PciExpressLib implementation To: Marcin Wojtas Cc: edk2-devel-groups-io , Leif Lindholm , =?UTF-8?B?SmFuIETEhWJyb8Wb?= , Grzegorz Jaszczyk , Kostya Porotchkin , Jici Gao , Rebecca Cran , Mark Kettenis Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 24 May 2019 at 16:28, Marcin Wojtas wrote: > > pt., 24 maj 2019 o 15:08 Ard Biesheuvel napis= a=C5=82(a): > > > > On Fri, 24 May 2019 at 15:03, Marcin Wojtas wrote: > > > > > > pt., 24 maj 2019 o 14:50 Ard Biesheuvel n= apisa=C5=82(a): > > > > > > > > On Mon, 20 May 2019 at 17:27, Marcin Wojtas wrote= : > > > > > > > > > > From: Ard Biesheuvel > > > > > > > > > > Implement a special version of PciExpressLib that takes the quirk= y > > > > > nature of the Synopsys Designware PCIe IP into account. In partic= ular, > > > > > we need to ignore config space accesses to all devices on the fir= st > > > > > bus except device 0, because the broadcast nature of type 0 confi= guration > > > > > cycles will result in whatever device is in the slot to appear at= each > > > > > of the 32 device positions. > > > > > > > > > > > > > I never bothered to implement multisegment support for this SoC, si= nce > > > > MacchiatoBin has only one segment wired up, but since your interest= is > > > > in generic support, it might make sense to drop this patch and > > > > implement PciSegmentLib instead (without depending on any of the ot= her > > > > library classes that the generic PciExpressLib depends on) > > > > > > > > > > This was (and still is) my plan, but I've been having some serious > > > time shortages for extra development. In order not to postpone this > > > support any longer I prefer to get merged, what I have and possibly > > > rework on top. > > > > > > About depending on a generic PciExpressLib - do you mean I can filter > > > out devices from bus0 in PciSegmentLib? > > > > > > > Yes, please look at Silicon/Socionext/SynQuacer/Library/SynQuacerPciSeg= mentLib > > > > If you follow the same approach, you no longer need PciLib or > > PciExpressLib, it is all flattened into PciSegmentLib. > > For PciLib I use MdePkg implementation, but if that could be dropped > that's good. I saw your library and it would be perfect for reusing on > Armada, with one difference: PciSegmentLibGetConfigBase. > > 1. As a first step I could reuse Synquacer library using single base > in PciSegmentLibGetConfigBase (PcdPciExpressBaseAddress) as a stub, > for extending later. > > 2. Afterwards (i.e. in some next patchset) I'd like to use my board > description infrastructure for obtaining config space base addresses. > How about following solution: > - add PciSegmentLib constructor routine, where I'd create a global > array with config space addesses > - add dispatching for it in PciSegmentLibGetConfigBase? > This sounds like a reasonable approach, yes. > Looking forward to your feedback. Other than that - do you have any > remarks to the rest of the patches in v2? > The rest looks fine.