* [platforms: PATCH 1/6] Marvell/Library: ComPhyLib: Configure SATA, SGMII and SFI in ARM-TF
2018-07-13 14:09 [platforms: PATCH 0/6] Armada7k8k ComPhy rework Marcin Wojtas
@ 2018-07-13 14:09 ` Marcin Wojtas
2018-07-13 14:22 ` Ard Biesheuvel
2018-07-13 14:09 ` [platforms: PATCH 2/6] Marvell/Library: ComPhyLib: Configure PCIE " Marcin Wojtas
` (5 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Marcin Wojtas @ 2018-07-13 14:09 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Replace all ComPhy initialization with appropriate smc calls. It will
result with triggering synchronous exception that is handled by Secure
Monitor code in EL3. Then the Secure Monitor code will dispatch each smc
call (by parsing the smc function identifier) and trigger appropriate
ComPhy initialization.
In this commit the speeds description used in .dsc files and the
ComPhyLib were aligned to the ones used in EL3.
This patch reworks serdes for: SATA, SGMII, HS-SGMII and SFI interfaces.
The next interfaces will be addressed in upcoming commits.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 18 +-
Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 1 +
Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 50 +-
Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 769 ++------------------
Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 13 +-
5 files changed, 103 insertions(+), 748 deletions(-)
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
index a9d67a2..fbbeee6 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -601,16 +601,14 @@
################################################################################
[Defines]
# ComPhy speed
- DEFINE CP_1_25G = 0x1
- DEFINE CP_1_5G = 0x2
- DEFINE CP_2_5G = 0x3
- DEFINE CP_3G = 0x4
- DEFINE CP_3_125G = 0x5
- DEFINE CP_5G = 0x6
- DEFINE CP_5_15625G = 0x7
- DEFINE CP_6G = 0x8
- DEFINE CP_6_25G = 0x9
- DEFINE CP_10_3125G = 0xA
+ DEFINE CP_1_25G = 0x0
+ DEFINE CP_2_5G = 0x1
+ DEFINE CP_3_125G = 0x2
+ DEFINE CP_5G = 0x3
+ DEFINE CP_5_15625G = 0x4
+ DEFINE CP_6G = 0x5
+ DEFINE CP_10_3125G = 0x6
+ DEFINE CP_DEFAULT = 0x3f
# ComPhy type
DEFINE CP_UNCONNECTED = 0x0
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
index f36c701..7a72203 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
@@ -47,6 +47,7 @@
[LibraryClasses]
ArmLib
+ ArmSmcLib
DebugLib
MemoryAllocationLib
PcdLib
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
index 090116d..34c1e9b 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
@@ -61,20 +61,17 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lane_struct[id].InvFlag = (UINT8 *)GET_LANE_SPEED(id); \
}
-/***** ComPhy *****/
-#define COMPHY_SPEED_ERROR 0
-#define COMPHY_SPEED_1_25G 1
-#define COMPHY_SPEED_1_5G 2
-#define COMPHY_SPEED_2_5G 3
-#define COMPHY_SPEED_3G 4
-#define COMPHY_SPEED_3_125G 5
-#define COMPHY_SPEED_5G 6
-#define COMPHY_SPEED_5_15625G 7
-#define COMPHY_SPEED_6G 8
-#define COMPHY_SPEED_6_25G 9
-#define COMPHY_SPEED_10_3125G 10
-#define COMPHY_SPEED_MAX 11
+#define COMPHY_SPEED_1_25G 0
+#define COMPHY_SPEED_2_5G 1
+#define COMPHY_SPEED_3_125G 2
+#define COMPHY_SPEED_5G 3
+#define COMPHY_SPEED_5_15625G 4
+#define COMPHY_SPEED_6G 5
+#define COMPHY_SPEED_10_3125G 6
+#define COMPHY_SPEED_MAX 7
#define COMPHY_SPEED_INVALID 0xff
+/* The default speed for IO with fixed known speed */
+#define COMPHY_SPEED_DEFAULT 0x3F
#define COMPHY_TYPE_UNCONNECTED 0
#define COMPHY_TYPE_PCIE0 1
@@ -103,6 +100,33 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define COMPHY_TYPE_MAX 24
#define COMPHY_TYPE_INVALID 0xff
+#define COMPHY_SATA_MODE 0x1
+#define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */
+#define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */
+#define COMPHY_USB3H_MODE 0x4
+#define COMPHY_USB3D_MODE 0x5
+#define COMPHY_PCIE_MODE 0x6
+#define COMPHY_RXAUI_MODE 0x7
+#define COMPHY_XFI_MODE 0x8
+#define COMPHY_SFI_MODE 0x9
+#define COMPHY_USB3_MODE 0xa
+#define COMPHY_AP_MODE 0xb
+
+/* Comphy unit index macro */
+#define COMPHY_UNIT_ID0 0
+#define COMPHY_UNIT_ID1 1
+#define COMPHY_UNIT_ID2 2
+#define COMPHY_UNIT_ID3 3
+
+/* Firmware related definitions used for SMC calls */
+#define MV_SIP_COMPHY_POWER_ON 0x82000001
+#define MV_SIP_COMPHY_POWER_OFF 0x82000002
+#define MV_SIP_COMPHY_PLL_LOCK 0x82000003
+
+#define COMPHY_FW_FORMAT(mode, idx, speeds) \
+ ((mode << 12) | (idx << 8) | (speeds << 2))
+
+
#define COMPHY_POLARITY_NO_INVERT 0
#define COMPHY_POLARITY_TXD_INVERT 1
#define COMPHY_POLARITY_RXD_INVERT 2
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
index 5e0ebf6..4b8b27a 100755
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
@@ -33,8 +33,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "ComPhyLib.h"
+
+#include <Library/ArmSmcLib.h>
#include <Library/SampleAtResetLib.h>
+#include <IndustryStandard/ArmStdSmc.h>
+
#define SD_LANE_ADDR_WIDTH 0x1000
#define HPIPE_ADDR_OFFSET 0x800
#define COMPHY_ADDR_LANE_WIDTH 0x28
@@ -796,274 +800,6 @@ ComPhySataMacPowerDown (
STATIC
VOID
-ComPhySataRFUConfiguration (
- IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
- IN EFI_PHYSICAL_ADDRESS SdIpAddr
-)
-{
- UINT32 Mask, Data;
-
- /* RFU configurations - hard reset ComPhy */
- Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
- Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
- Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
- Data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
- Mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
- Data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
- Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
- Data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
- RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
-
- /* Set select Data width 40Bit - SATA mode only */
- RegSet (ComPhyAddr + COMMON_PHY_CFG6_REG,
- 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET, COMMON_PHY_CFG6_IF_40_SEL_MASK);
-
- /* Release from hard reset in SD external */
- Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
- Data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
- Mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- Data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
- RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask);
-
- /* Wait 1ms - until band gap and ref clock ready */
- MicroSecondDelay (1000);
- MemoryFence ();
-}
-
-STATIC
-VOID
-ComPhySataPhyConfiguration (
- IN EFI_PHYSICAL_ADDRESS HpipeAddr
-)
-{
- UINT32 Mask, Data;
-
- /* Set reference clock to comes from group 1 - choose 25Mhz */
- RegSet (HpipeAddr + HPIPE_MISC_REG,
- 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, HPIPE_MISC_REFCLK_SEL_MASK);
-
- /* Reference frequency select set 1 (for SATA = 25Mhz) */
- Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
- Data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
-
- /* PHY mode select (set SATA = 0x0 */
- Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
- Data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
- RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
-
- /* Set max PHY generation setting - 6Gbps */
- RegSet (HpipeAddr + HPIPE_INTERFACE_REG,
- 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET, HPIPE_INTERFACE_GEN_MAX_MASK);
-
- /* Set select Data width 40Bit (SEL_BITS[2:0]) */
- RegSet (HpipeAddr + HPIPE_LOOPBACK_REG,
- 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
-}
-
-STATIC
-VOID
-ComPhySataSetAnalogParameters (
- IN EFI_PHYSICAL_ADDRESS HpipeAddr,
- IN EFI_PHYSICAL_ADDRESS SdIpAddr
-)
-{
- UINT32 Mask, Data;
-
- /* Hpipe Generation 1 settings 1 */
- Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |
- HPIPE_GX_SET1_RX_SELMUPP_MASK |
- HPIPE_GX_SET1_RX_SELMUFI_MASK |
- HPIPE_GX_SET1_RX_SELMUFF_MASK |
- HPIPE_GX_SET1_RX_DIGCK_DIV_MASK;
- Data = (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) |
- (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) |
- (0x1 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET1_REG, ~Mask, Data);
-
- /* Hpipe Generation 1 settings 3 */
- Mask = HPIPE_GX_SET3_FFE_CAP_SEL_MASK |
- HPIPE_GX_SET3_FFE_RES_SEL_MASK |
- HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK |
- HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK |
- HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK;
- Data = 0xf |
- (0x2 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) |
- (0x1 << HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET) |
- (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) |
- (0x1 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET3_REG, ~Mask, Data);
-
- /* Hpipe Generation 2 settings 1 */
- Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |
- HPIPE_GX_SET1_RX_SELMUPP_MASK |
- HPIPE_GX_SET1_RX_SELMUFI_MASK |
- HPIPE_GX_SET1_RX_SELMUFF_MASK |
- HPIPE_GX_SET1_RX_DIGCK_DIV_MASK;
- Data = (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) |
- (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) |
- (0x1 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_G2_SET1_REG, ~Mask, Data);
-
- /* Hpipe Generation 3 settings 1 */
- Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |
- HPIPE_GX_SET1_RX_SELMUPP_MASK |
- HPIPE_GX_SET1_RX_SELMUFI_MASK |
- HPIPE_GX_SET1_RX_SELMUFF_MASK |
- HPIPE_GX_SET1_RX_DFE_EN_MASK |
- HPIPE_GX_SET1_RX_DIGCK_DIV_MASK |
- HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_MASK;
- Data = 0x2 |
- (0x2 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) |
- (0x3 << HPIPE_GX_SET1_RX_SELMUFI_OFFSET) |
- (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) |
- (0x1 << HPIPE_GX_SET1_RX_DFE_EN_OFFSET) |
- (0x2 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data);
-
- /* DTL Control */
- Mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK |
- HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK |
- HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK |
- HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK |
- HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK |
- HPIPE_PWR_CTR_DTL_CLK_MODE_MASK |
- HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK;
- Data = 0x1 |
- (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) |
- (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) |
- (0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) |
- (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) |
- (0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) |
- (0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~Mask, Data);
-
- /* Trigger sampler enable pulse (by toggling the bit) */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
- ~HPIPE_SAMPLER_MASK,
- 0x1 << HPIPE_SAMPLER_OFFSET
- );
- MmioAnd32 (
- HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
- ~HPIPE_SAMPLER_MASK
- );
-
- /* VDD Calibration Control 3 */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_VDD_CAL_CTRL_REG,
- ~HPIPE_EXT_SELLV_RXSAMPL_MASK,
- 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET
- );
-
- /* DFE Resolution Control */
- MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK);
-
- /* DFE F3-F5 Coefficient Control */
- MmioAnd32 (
- HpipeAddr + HPIPE_DFE_F3_F5_REG,
- ~(HPIPE_DFE_F3_F5_DFE_EN_MASK | HPIPE_DFE_F3_F5_DFE_CTRL_MASK)
- );
-
- /* Hpipe Generation 3 settings 3 */
- Mask = HPIPE_GX_SET3_FFE_CAP_SEL_MASK |
- HPIPE_GX_SET3_FFE_RES_SEL_MASK |
- HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK |
- HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK |
- HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK;
- Data = 0xf |
- (0x4 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) |
- (0x1 << HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET) |
- (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) |
- (0x3 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET3_REG, ~Mask, Data);
-
- /* Hpipe Generation 3 settings 4 */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_G3_SET4_REG,
- ~HPIPE_GX_SET4_DFE_RES_MASK,
- 0x2 << HPIPE_GX_SET4_DFE_RES_OFFSET
- );
-
- /* Offset Phase Control - force offset and toggle 'valid' bit */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_PHASE_CONTROL_REG,
- ~(HPIPE_OS_PH_OFFSET_MASK | HPIPE_OS_PH_OFFSET_FORCE_MASK),
- 0x5c | (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
- );
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_PHASE_CONTROL_REG,
- ~HPIPE_OS_PH_VALID_MASK,
- 0x1 << HPIPE_OS_PH_VALID_OFFSET
- );
- MmioAnd32 (
- HpipeAddr + HPIPE_PHASE_CONTROL_REG,
- ~HPIPE_OS_PH_VALID_MASK
- );
-
- /* Set G1 TX amplitude and TX post emphasis value */
- Mask = HPIPE_GX_SET0_TX_AMP_MASK |
- HPIPE_GX_SET0_TX_AMP_ADJ_MASK |
- HPIPE_GX_SET0_TX_EMPH1_MASK |
- HPIPE_GX_SET0_TX_EMPH1_EN_MASK;
- Data = (0x8 << HPIPE_GX_SET0_TX_AMP_OFFSET) |
- (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) |
- (0x1 << HPIPE_GX_SET0_TX_EMPH1_OFFSET) |
- (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET0_REG, ~Mask, Data);
-
- /* Set G2 TX amplitude and TX post emphasis value */
- Mask = HPIPE_GX_SET0_TX_AMP_MASK |
- HPIPE_GX_SET0_TX_AMP_ADJ_MASK |
- HPIPE_GX_SET0_TX_EMPH1_MASK |
- HPIPE_GX_SET0_TX_EMPH1_EN_MASK;
- Data = (0xa << HPIPE_GX_SET0_TX_AMP_OFFSET) |
- (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) |
- (0x2 << HPIPE_GX_SET0_TX_EMPH1_OFFSET) |
- (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_G2_SET0_REG, ~Mask, Data);
-
- /* Set G3 TX amplitude and TX post emphasis value */
- Mask = HPIPE_GX_SET0_TX_AMP_MASK |
- HPIPE_GX_SET0_TX_AMP_ADJ_MASK |
- HPIPE_GX_SET0_TX_EMPH1_MASK |
- HPIPE_GX_SET0_TX_EMPH1_EN_MASK |
- HPIPE_GX_SET0_TX_SLEW_RATE_SEL_MASK |
- HPIPE_GX_SET0_TX_SLEW_CTRL_EN_MASK;
- Data = (0xe << HPIPE_GX_SET0_TX_AMP_OFFSET) |
- (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) |
- (0x6 << HPIPE_GX_SET0_TX_EMPH1_OFFSET) |
- (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET) |
- (0x4 << HPIPE_GX_SET0_TX_SLEW_RATE_SEL_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET0_REG, ~Mask, Data);
-
- /* SERDES External Configuration 2 register - enable spread spectrum clock */
- MmioOr32 (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK);
-
- /* DFE reset sequence */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_PWR_CTR_REG,
- ~HPIPE_PWR_CTR_RST_DFE_MASK,
- 0x1
- );
- MmioAnd32 (
- HpipeAddr + HPIPE_PWR_CTR_REG,
- ~HPIPE_PWR_CTR_RST_DFE_MASK
- );
-
- /* SW reset for interupt logic */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_PWR_CTR_REG,
- ~HPIPE_PWR_CTR_SFT_RST_MASK,
- 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET
- );
- MmioAnd32 (
- HpipeAddr + HPIPE_PWR_CTR_REG,
- ~HPIPE_PWR_CTR_SFT_RST_MASK
- );
-}
-
-STATIC
-VOID
ComPhySataPhyPowerUp (
IN EFI_PHYSICAL_ADDRESS SataBase
)
@@ -1106,30 +842,26 @@ ComPhySataPhyPowerUp (
STATIC
EFI_STATUS
-ComPhySataCheckPll (
- IN EFI_PHYSICAL_ADDRESS HpipeAddr,
- IN EFI_PHYSICAL_ADDRESS SdIpAddr
-)
+ComPhySmc (
+ IN UINT32 FunctionId,
+ EFI_PHYSICAL_ADDRESS ComPhyBaseAddr,
+ IN UINT32 Lane,
+ IN UINT32 Mode
+ )
{
- EFI_STATUS Status = EFI_SUCCESS;
- UINT32 Data,Mask;
- IN EFI_PHYSICAL_ADDRESS Addr;
+ ARM_SMC_ARGS SmcRegs = {0};
- Addr = SdIpAddr + SD_EXTERNAL_STATUS0_REG;
- Data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & SD_EXTERNAL_STATUS0_PLL_RX_MASK;
- Mask = Data;
- Data = PollingWithTimeout (Addr, Data, Mask, 15000);
+ SmcRegs.Arg0 = FunctionId;
+ SmcRegs.Arg1 = (UINTN)ComPhyBaseAddr;
+ SmcRegs.Arg2 = Lane;
+ SmcRegs.Arg3 = Mode;
+ ArmCallSmc (&SmcRegs);
- if (Data != 0) {
- DEBUG((DEBUG_INFO, "ComPhy: Read from reg = %p - value = 0x%x\n",
- HpipeAddr + HPIPE_LANE_STATUS0_REG, Data));
- DEBUG((DEBUG_ERROR, "ComPhy: SD_EXTERNAL_STATUS0_PLL_TX is %d, SD_EXTERNAL_STATUS0_PLL_RX is %d\n",
- (Data & SD_EXTERNAL_STATUS0_PLL_TX_MASK),
- (Data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)));
- Status = EFI_D_ERROR;
+ if (SmcRegs.Arg0 != 0) {
+ return EFI_DEVICE_ERROR;
}
- return Status;
+ return EFI_SUCCESS;
}
STATIC
@@ -1143,9 +875,6 @@ ComPhySataPowerUp (
)
{
EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
- EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane);
- EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
DEBUG ((DEBUG_INFO, "ComPhySata: Initialize SATA PHYs\n"));
@@ -1153,123 +882,29 @@ ComPhySataPowerUp (
ComPhySataMacPowerDown (Desc[ChipId].SoC->AhciBaseAddress);
- DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
-
- ComPhySataRFUConfiguration (ComPhyAddr, SdIpAddr);
-
- DEBUG((DEBUG_INFO, "ComPhy: stage: Comphy configuration\n"));
-
- ComPhySataPhyConfiguration (HpipeAddr);
-
- DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n"));
-
- ComPhySataSetAnalogParameters (HpipeAddr, SdIpAddr);
-
- DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n"));
+ Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
+ ComPhyBase,
+ Lane,
+ COMPHY_FW_FORMAT (COMPHY_SATA_MODE,
+ Desc[ChipId].SoC->AhciId,
+ COMPHY_SPEED_DEFAULT));
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
ComPhySataPhyPowerUp (Desc[ChipId].SoC->AhciBaseAddress);
- DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n"));
-
- Status = ComPhySataCheckPll (HpipeAddr, SdIpAddr);
-
- return Status;
-}
-
-STATIC
-VOID
-ComPhySgmiiRFUConfiguration (
- IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
- IN EFI_PHYSICAL_ADDRESS SdIpAddr,
- IN UINT32 SgmiiSpeed
-)
-{
- UINT32 Mask, Data;
-
- Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
- Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
- Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
- Data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
- RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
-
- /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
- Mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
- Data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
- Mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
- Mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
- if (SgmiiSpeed == COMPHY_SPEED_1_25G) {
- Data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
- Data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
- } else {
- /* 3.125G */
- Data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
- Data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
+ Status = ComPhySmc (MV_SIP_COMPHY_PLL_LOCK,
+ ComPhyBase,
+ Lane,
+ COMPHY_FW_FORMAT (COMPHY_SATA_MODE,
+ Desc[ChipId].SoC->AhciId,
+ COMPHY_SPEED_DEFAULT));
+ if (EFI_ERROR (Status)) {
+ return Status;
}
- Mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
- Data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
- Mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
- Data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
- Mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
- Data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
- RegSet (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, Data, Mask);
-
- /* Release from hard reset */
- Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
- Data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
- Mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- Data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
- Mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
- Data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
- RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask);
-
- /* Release from hard reset */
- Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
- Data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
- Mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- Data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
- RegSet (SdIpAddr+ SD_EXTERNAL_CONFIG1_REG, Data, Mask);
- /* Wait 1ms - until band gap and ref clock ready */
- MicroSecondDelay (1000);
- MemoryFence ();
-}
-
-STATIC
-VOID
-ComPhySgmiiPhyConfiguration (
- IN EFI_PHYSICAL_ADDRESS HpipeAddr
-)
-{
- UINT32 Mask, Data;
-
- /* Set reference clock */
- Mask = HPIPE_MISC_REFCLK_SEL_MASK;
- Data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
- RegSet (HpipeAddr + HPIPE_MISC_REG, Data, Mask);
-
- /* Power and PLL Control */
- Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
- Data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
- Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
- Data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
- RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
-
- /* Loopback register */
- Mask = HPIPE_LOOPBACK_SEL_MASK;
- Data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET;
- RegSet (HpipeAddr + HPIPE_LOOPBACK_REG, Data, Mask);
-
- /* Rx control 1 */
- Mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
- Data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
- Mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
- Data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
- RegSet (HpipeAddr + HPIPE_RX_CONTROL_1_REG, Data, Mask);
-
- /* DTL Control */
- Mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
- Data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
- RegSet (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, Data, Mask);
+ return Status;
}
STATIC
@@ -1331,321 +966,6 @@ ComPhyEthCommonRFUPowerUp (
}
STATIC
-UINTN
-ComPhySgmiiPowerUp (
- IN UINT32 Lane,
- IN UINT32 SgmiiSpeed,
- IN EFI_PHYSICAL_ADDRESS HpipeBase,
- IN EFI_PHYSICAL_ADDRESS ComPhyBase
- )
-{
- EFI_STATUS Status = EFI_SUCCESS;
- EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
- EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane);
- EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
-
- DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
-
- ComPhySgmiiRFUConfiguration (ComPhyAddr, SdIpAddr, SgmiiSpeed);
-
- DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
-
- ComPhySgmiiPhyConfiguration (HpipeAddr);
-
- /* Set analog paramters from ETP(HW) - for now use the default data */
- DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n"));
-
- RegSet (HpipeAddr + HPIPE_G1_SET0_REG,
- 0x1 << HPIPE_GX_SET0_TX_EMPH1_OFFSET, HPIPE_GX_SET0_TX_EMPH1_MASK);
-
- DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx,Rx\n"));
-
- Status = ComPhyEthCommonRFUPowerUp (SdIpAddr);
-
- return Status;
-}
-
-STATIC
-VOID
-ComPhySfiRFUConfiguration (
- IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
- IN EFI_PHYSICAL_ADDRESS SdIpAddr
-)
-{
- UINT32 Mask, Data;
-
- MmioAndThenOr32 (
- ComPhyAddr + COMMON_PHY_CFG1_REG,
- ~(COMMON_PHY_CFG1_PWR_UP_MASK | COMMON_PHY_CFG1_PIPE_SELECT_MASK),
- COMMON_PHY_CFG1_PWR_UP_MASK
- );
-
- /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
- Mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK |
- SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK |
- SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK |
- SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK |
- SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK |
- SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
- Data = (0xe << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) |
- (0xe << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET);
- MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, ~Mask, Data);
-
- /* Release from hard reset */
- Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK |
- SD_EXTERNAL_CONFIG1_RESET_CORE_MASK |
- SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
- Data = SD_EXTERNAL_CONFIG1_RESET_IN_MASK |
- SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, ~Mask, Data);
-
- /* Wait 1ms - until band gap and ref clock are ready */
- MicroSecondDelay (1000);
- MemoryFence ();
-}
-
-STATIC
-VOID
-ComPhySfiPhyConfiguration (
- IN EFI_PHYSICAL_ADDRESS HpipeAddr,
- IN UINT32 SfiSpeed
-)
-{
- UINT32 Mask, Data;
-
- /* Set reference clock */
- Mask = HPIPE_MISC_ICP_FORCE_MASK | HPIPE_MISC_REFCLK_SEL_MASK;
- Data = (SfiSpeed == COMPHY_SPEED_5_15625G) ?
- (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) : (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_MISC_REG, ~Mask, Data);
-
- /* Power and PLL Control */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_PWR_PLL_REG,
- ~(HPIPE_PWR_PLL_REF_FREQ_MASK | HPIPE_PWR_PLL_PHY_MODE_MASK),
- 0x1 | (0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
- );
-
- /* Loopback register */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_LOOPBACK_REG,
- ~HPIPE_LOOPBACK_SEL_MASK,
- 0x1 << HPIPE_LOOPBACK_SEL_OFFSET
- );
-
- /* Rx control 1 */
- MmioOr32 (
- HpipeAddr + HPIPE_RX_CONTROL_1_REG,
- HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK | HPIPE_RX_CONTROL_1_CLK8T_EN_MASK
- );
-
- /* DTL Control */
- MmioOr32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
-
- /* Transmitter/Receiver Speed Divider Force */
- if (SfiSpeed == COMPHY_SPEED_5_15625G) {
- Mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK |
- HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK |
- HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK |
- HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK;
- Data = (1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) |
- (1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) |
- (1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) |
- (1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_SPD_DIV_FORCE_REG, ~Mask, Data);
- } else {
- MmioOr32 (HpipeAddr + HPIPE_SPD_DIV_FORCE_REG, HPIPE_TXDIGCK_DIV_FORCE_MASK);
- }
-}
-
-STATIC
-VOID
-ComPhySfiSetAnalogParameters (
- IN EFI_PHYSICAL_ADDRESS HpipeAddr,
- IN EFI_PHYSICAL_ADDRESS SdIpAddr,
- IN UINT32 SfiSpeed
-)
-{
- UINT32 Mask, Data;
-
- /* SERDES External Configuration 2 */
- MmioOr32 (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
-
- /* DFE Resolution control */
- MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK);
-
- /* Generation 1 setting_0 */
- if (SfiSpeed == COMPHY_SPEED_5_15625G) {
- Mask = HPIPE_GX_SET0_TX_EMPH1_MASK;
- Data = 0x6 << HPIPE_GX_SET0_TX_EMPH1_OFFSET;
- } else {
- Mask = HPIPE_GX_SET0_TX_AMP_MASK | HPIPE_GX_SET0_TX_EMPH1_MASK;
- Data = (0x1c << HPIPE_GX_SET0_TX_AMP_OFFSET) | (0xe << HPIPE_GX_SET0_TX_EMPH1_OFFSET);
- }
- MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET0_REG, ~Mask, Data);
-
- /* Generation 1 setting 2 */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_GX_SET2_REG,
- ~HPIPE_GX_SET2_TX_EMPH0_MASK,
- HPIPE_GX_SET2_TX_EMPH0_EN_MASK
- );
-
- /* Transmitter Slew Rate Control register */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_TX_REG1_REG,
- ~(HPIPE_TX_REG1_TX_EMPH_RES_MASK | HPIPE_TX_REG1_SLC_EN_MASK),
- (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) | (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
- );
-
- /* Impedance Calibration Control register */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_CAL_REG1_REG,
- ~(HPIPE_CAL_REG_1_EXT_TXIMP_MASK | HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK),
- (0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) | HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK
- );
-
- /* Generation 1 setting 5 */
- MmioAnd32 (HpipeAddr + HPIPE_G1_SET5_REG, ~HPIPE_GX_SET5_ICP_MASK);
-
- /* Generation 1 setting 1 */
- if (SfiSpeed == COMPHY_SPEED_5_15625G) {
- Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK | HPIPE_GX_SET1_RX_SELMUPP_MASK;
- Data = 0x1 | (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET);
- } else {
- Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |
- HPIPE_GX_SET1_RX_SELMUPP_MASK |
- HPIPE_GX_SET1_RX_SELMUFI_MASK |
- HPIPE_GX_SET1_RX_SELMUFF_MASK |
- HPIPE_GX_SET1_RX_DIGCK_DIV_MASK;
- Data = 0x2 |
- (0x2 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) |
- (0x1 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) |
- (0x3 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET);
- }
- MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET1_REG, ~Mask, Data);
- MmioOr32 (HpipeAddr + HPIPE_G1_SET1_REG, HPIPE_GX_SET1_RX_DFE_EN_MASK);
-
- /* DFE F3-F5 Coefficient Control */
- MmioAnd32 (
- HpipeAddr + HPIPE_DFE_F3_F5_REG,
- ~(HPIPE_DFE_F3_F5_DFE_EN_MASK | HPIPE_DFE_F3_F5_DFE_CTRL_MASK)
- );
-
- /* Configure Generation 1 setting 4 (DFE) */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_G1_SET4_REG,
- ~HPIPE_GX_SET4_DFE_RES_MASK,
- 0x1 << HPIPE_GX_SET4_DFE_RES_OFFSET
- );
-
- /* Generation 1 setting 3 */
- MmioOr32 (HpipeAddr + HPIPE_G1_SET3_REG, HPIPE_GX_SET3_FBCK_SEL_MASK);
-
- if (SfiSpeed == COMPHY_SPEED_5_15625G) {
- /* Force FFE (Feed Forward Equalization) to 5G */
- Mask = HPIPE_GX_SET3_FFE_CAP_SEL_MASK |
- HPIPE_GX_SET3_FFE_RES_SEL_MASK |
- HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK;
- Data = 0xf | (0x4 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) | HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK;
- MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET3_REG, ~Mask, Data);
- }
-
- /* Configure RX training timer */
- MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_5_REG, ~HPIPE_RX_TRAIN_TIMER_MASK, 0x13);
-
- /* Enable TX train peak to peak hold */
- MmioOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_0_REG, HPIPE_TX_TRAIN_P2P_HOLD_MASK);
-
- /* Configure TX preset index */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_TX_PRESET_INDEX_REG,
- ~HPIPE_TX_PRESET_INDEX_MASK,
- 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET
- );
-
- /* Disable pattern lock lost timeout */
- MmioAnd32 (HpipeAddr + HPIPE_FRAME_DETECT_CTRL_3_REG, ~HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK);
-
- /* Configure TX training pattern and TX training 16bit auto */
- MmioOr32 (
- HpipeAddr + HPIPE_TX_TRAIN_REG,
- HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK | HPIPE_TX_TRAIN_PAT_SEL_MASK
- );
-
- /* Configure training pattern number */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_FRAME_DETECT_CTRL_0_REG,
- ~HPIPE_TRAIN_PAT_NUM_MASK,
- 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET
- );
-
- /* Configure differential manchester encoder to ethernet mode */
- MmioOr32 (HpipeAddr + HPIPE_DME_REG, HPIPE_DME_ETHERNET_MODE_MASK);
-
- /* Configure VDD Continuous Calibration */
- MmioOr32 (HpipeAddr + HPIPE_VDD_CAL_0_REG, HPIPE_CAL_VDD_CONT_MODE_MASK);
-
- /* Configure sampler gain */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
- ~HPIPE_RX_SAMPLER_OS_GAIN_MASK,
- 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET
- );
-
- /* Trigger sampler enable pulse (by toggling the bit) */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
- ~HPIPE_SAMPLER_MASK,
- 0x1 << HPIPE_SAMPLER_OFFSET
- );
- MmioAnd32 (
- HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
- ~HPIPE_SAMPLER_MASK
- );
-
- /* VDD calibration control */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_VDD_CAL_CTRL_REG,
- ~HPIPE_EXT_SELLV_RXSAMPL_MASK,
- 0x1a << HPIPE_EXT_SELLV_RXSAMPL_OFFSET
- );
-}
-
-STATIC
-EFI_STATUS
-ComPhySfiPowerUp (
- IN UINT32 Lane,
- IN EFI_PHYSICAL_ADDRESS HpipeBase,
- IN EFI_PHYSICAL_ADDRESS ComPhyBase,
- IN UINT32 SfiSpeed
- )
-{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
- EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane);
- EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
-
- DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
-
- ComPhySfiRFUConfiguration (ComPhyAddr, SdIpAddr);
-
- DEBUG ((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
-
- ComPhySfiPhyConfiguration (HpipeAddr, SfiSpeed);
-
- DEBUG ((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n"));
-
- ComPhySfiSetAnalogParameters (HpipeAddr, SdIpAddr, SfiSpeed);
-
- DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx,Rx\n"));
-
- Status = ComPhyEthCommonRFUPowerUp (SdIpAddr);
-
- return Status;
-}
-
-STATIC
EFI_STATUS
ComPhyRxauiRFUConfiguration (
IN UINT32 Lane,
@@ -1945,11 +1265,20 @@ ComPhyCp110Init (
case COMPHY_TYPE_SGMII1:
case COMPHY_TYPE_SGMII2:
case COMPHY_TYPE_SGMII3:
- Status = ComPhySgmiiPowerUp(Lane, PtrComPhyMap->Speed, HpipeBaseAddr,
- ComPhyBaseAddr);
+ Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
+ PtrChipCfg->ComPhyBaseAddr,
+ Lane,
+ COMPHY_FW_FORMAT (COMPHY_SGMII_MODE,
+ (PtrComPhyMap->Type - COMPHY_TYPE_SGMII0),
+ PtrComPhyMap->Speed));
break;
case COMPHY_TYPE_SFI:
- Status = ComPhySfiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr, PtrComPhyMap->Speed);
+ Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
+ PtrChipCfg->ComPhyBaseAddr,
+ Lane,
+ COMPHY_FW_FORMAT (COMPHY_SFI_MODE,
+ COMPHY_UNIT_ID0,
+ PtrComPhyMap->Speed));
break;
case COMPHY_TYPE_RXAUI0:
case COMPHY_TYPE_RXAUI1:
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
index 2ef9af4..b3a8c10 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
@@ -42,9 +42,9 @@ CHAR16 * TypeStringTable [] = {L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2",
L"USB3_DEVICE", L"XAUI0", L"XAUI1", L"XAUI2",
L"XAUI3", L"RXAUI0", L"RXAUI1", L"SFI"};
-CHAR16 * SpeedStringTable [] = {L"-", L"1.25 Gbps", L"1.5 Gbps", L"2.5 Gbps",
- L"3.0 Gbps", L"3.125 Gbps", L"5 Gbps", L"5.156 Gbps",
- L"6 Gbps", L"6.25 Gbps", L"10.31 Gbps"};
+CHAR16 * SpeedStringTable [] = {L"1.25 Gbps", L"2.5 Gbps", L"3.125 Gbps",
+ L"5 Gbps", L"5.156 Gbps", L"6 Gbps",
+ L"10.31 Gbps"};
CHIP_COMPHY_CONFIG ChipCfgTbl[] = {
{
@@ -129,7 +129,11 @@ GetSpeedString (
)
{
- if (Speed < 0 || Speed > 10) {
+ if (Speed == COMPHY_SPEED_DEFAULT) {
+ return L"default";
+ }
+
+ if (Speed < 0 || Speed > COMPHY_SPEED_MAX) {
return L"invalid";
}
@@ -266,7 +270,6 @@ MvComPhyInit (
PtrChipCfg->MapData[Lane].Invert = LaneData[Index].InvFlag[Lane];
if ((PtrChipCfg->MapData[Lane].Speed == COMPHY_SPEED_INVALID) ||
- (PtrChipCfg->MapData[Lane].Speed == COMPHY_SPEED_ERROR) ||
(PtrChipCfg->MapData[Lane].Type == COMPHY_TYPE_INVALID)) {
DEBUG((DEBUG_ERROR, "ComPhy: No valid phy speed or type for lane %d, "
"setting lane as unconnected\n", Lane + 1));
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [platforms: PATCH 1/6] Marvell/Library: ComPhyLib: Configure SATA, SGMII and SFI in ARM-TF
2018-07-13 14:09 ` [platforms: PATCH 1/6] Marvell/Library: ComPhyLib: Configure SATA, SGMII and SFI in ARM-TF Marcin Wojtas
@ 2018-07-13 14:22 ` Ard Biesheuvel
0 siblings, 0 replies; 11+ messages in thread
From: Ard Biesheuvel @ 2018-07-13 14:22 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel@lists.01.org, Leif Lindholm, Nadav Haklai,
Jan Dąbroś, Grzegorz Jaszczyk
On 13 July 2018 at 16:09, Marcin Wojtas <mw@semihalf.com> wrote:
> From: Grzegorz Jaszczyk <jaz@semihalf.com>
>
> Replace all ComPhy initialization with appropriate smc calls. It will
> result with triggering synchronous exception that is handled by Secure
> Monitor code in EL3. Then the Secure Monitor code will dispatch each smc
> call (by parsing the smc function identifier) and trigger appropriate
> ComPhy initialization.
>
I think the gory details of how Secure Monitor calls are
architecturally designed can be omitted from this commit log, no?
> In this commit the speeds description used in .dsc files and the
> ComPhyLib were aligned to the ones used in EL3.
>
> This patch reworks serdes for: SATA, SGMII, HS-SGMII and SFI interfaces.
> The next interfaces will be addressed in upcoming commits.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 18 +-
> Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 1 +
> Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 50 +-
> Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 769 ++------------------
> Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 13 +-
> 5 files changed, 103 insertions(+), 748 deletions(-)
>
> diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> index a9d67a2..fbbeee6 100644
> --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> @@ -601,16 +601,14 @@
> ################################################################################
> [Defines]
> # ComPhy speed
> - DEFINE CP_1_25G = 0x1
> - DEFINE CP_1_5G = 0x2
> - DEFINE CP_2_5G = 0x3
> - DEFINE CP_3G = 0x4
> - DEFINE CP_3_125G = 0x5
> - DEFINE CP_5G = 0x6
> - DEFINE CP_5_15625G = 0x7
> - DEFINE CP_6G = 0x8
> - DEFINE CP_6_25G = 0x9
> - DEFINE CP_10_3125G = 0xA
> + DEFINE CP_1_25G = 0x0
> + DEFINE CP_2_5G = 0x1
> + DEFINE CP_3_125G = 0x2
> + DEFINE CP_5G = 0x3
> + DEFINE CP_5_15625G = 0x4
> + DEFINE CP_6G = 0x5
> + DEFINE CP_10_3125G = 0x6
> + DEFINE CP_DEFAULT = 0x3f
>
Can you put a comment here that these values are defined externally?
> # ComPhy type
> DEFINE CP_UNCONNECTED = 0x0
> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> index f36c701..7a72203 100644
> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
> @@ -47,6 +47,7 @@
>
> [LibraryClasses]
> ArmLib
> + ArmSmcLib
> DebugLib
> MemoryAllocationLib
> PcdLib
> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> index 090116d..34c1e9b 100644
> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> @@ -61,20 +61,17 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> lane_struct[id].InvFlag = (UINT8 *)GET_LANE_SPEED(id); \
> }
>
> -/***** ComPhy *****/
> -#define COMPHY_SPEED_ERROR 0
> -#define COMPHY_SPEED_1_25G 1
> -#define COMPHY_SPEED_1_5G 2
> -#define COMPHY_SPEED_2_5G 3
> -#define COMPHY_SPEED_3G 4
> -#define COMPHY_SPEED_3_125G 5
> -#define COMPHY_SPEED_5G 6
> -#define COMPHY_SPEED_5_15625G 7
> -#define COMPHY_SPEED_6G 8
> -#define COMPHY_SPEED_6_25G 9
> -#define COMPHY_SPEED_10_3125G 10
> -#define COMPHY_SPEED_MAX 11
> +#define COMPHY_SPEED_1_25G 0
> +#define COMPHY_SPEED_2_5G 1
> +#define COMPHY_SPEED_3_125G 2
> +#define COMPHY_SPEED_5G 3
> +#define COMPHY_SPEED_5_15625G 4
> +#define COMPHY_SPEED_6G 5
> +#define COMPHY_SPEED_10_3125G 6
> +#define COMPHY_SPEED_MAX 7
> #define COMPHY_SPEED_INVALID 0xff
> +/* The default speed for IO with fixed known speed */
> +#define COMPHY_SPEED_DEFAULT 0x3F
>
> #define COMPHY_TYPE_UNCONNECTED 0
> #define COMPHY_TYPE_PCIE0 1
> @@ -103,6 +100,33 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> #define COMPHY_TYPE_MAX 24
> #define COMPHY_TYPE_INVALID 0xff
>
> +#define COMPHY_SATA_MODE 0x1
> +#define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */
> +#define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */
> +#define COMPHY_USB3H_MODE 0x4
> +#define COMPHY_USB3D_MODE 0x5
> +#define COMPHY_PCIE_MODE 0x6
> +#define COMPHY_RXAUI_MODE 0x7
> +#define COMPHY_XFI_MODE 0x8
> +#define COMPHY_SFI_MODE 0x9
> +#define COMPHY_USB3_MODE 0xa
> +#define COMPHY_AP_MODE 0xb
> +
> +/* Comphy unit index macro */
> +#define COMPHY_UNIT_ID0 0
> +#define COMPHY_UNIT_ID1 1
> +#define COMPHY_UNIT_ID2 2
> +#define COMPHY_UNIT_ID3 3
> +
> +/* Firmware related definitions used for SMC calls */
> +#define MV_SIP_COMPHY_POWER_ON 0x82000001
> +#define MV_SIP_COMPHY_POWER_OFF 0x82000002
> +#define MV_SIP_COMPHY_PLL_LOCK 0x82000003
> +
> +#define COMPHY_FW_FORMAT(mode, idx, speeds) \
> + ((mode << 12) | (idx << 8) | (speeds << 2))
> +
> +
> #define COMPHY_POLARITY_NO_INVERT 0
> #define COMPHY_POLARITY_TXD_INVERT 1
> #define COMPHY_POLARITY_RXD_INVERT 2
Could we have a separate header for the Marvell SIP SMC call namespace?
> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> index 5e0ebf6..4b8b27a 100755
> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> @@ -33,8 +33,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> *******************************************************************************/
>
> #include "ComPhyLib.h"
> +
> +#include <Library/ArmSmcLib.h>
> #include <Library/SampleAtResetLib.h>
>
> +#include <IndustryStandard/ArmStdSmc.h>
> +
> #define SD_LANE_ADDR_WIDTH 0x1000
> #define HPIPE_ADDR_OFFSET 0x800
> #define COMPHY_ADDR_LANE_WIDTH 0x28
> @@ -796,274 +800,6 @@ ComPhySataMacPowerDown (
>
> STATIC
> VOID
> -ComPhySataRFUConfiguration (
> - IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
> - IN EFI_PHYSICAL_ADDRESS SdIpAddr
> -)
> -{
> - UINT32 Mask, Data;
> -
> - /* RFU configurations - hard reset ComPhy */
> - Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
> - Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
> - Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
> - Data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
> - Mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
> - Data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
> - Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
> - Data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
> - RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
> -
> - /* Set select Data width 40Bit - SATA mode only */
> - RegSet (ComPhyAddr + COMMON_PHY_CFG6_REG,
> - 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET, COMMON_PHY_CFG6_IF_40_SEL_MASK);
> -
> - /* Release from hard reset in SD external */
> - Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
> - Data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
> - Mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
> - Data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
> - RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask);
> -
> - /* Wait 1ms - until band gap and ref clock ready */
> - MicroSecondDelay (1000);
> - MemoryFence ();
> -}
> -
> -STATIC
> -VOID
> -ComPhySataPhyConfiguration (
> - IN EFI_PHYSICAL_ADDRESS HpipeAddr
> -)
> -{
> - UINT32 Mask, Data;
> -
> - /* Set reference clock to comes from group 1 - choose 25Mhz */
> - RegSet (HpipeAddr + HPIPE_MISC_REG,
> - 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, HPIPE_MISC_REFCLK_SEL_MASK);
> -
> - /* Reference frequency select set 1 (for SATA = 25Mhz) */
> - Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
> - Data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
> -
> - /* PHY mode select (set SATA = 0x0 */
> - Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
> - Data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
> - RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
> -
> - /* Set max PHY generation setting - 6Gbps */
> - RegSet (HpipeAddr + HPIPE_INTERFACE_REG,
> - 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET, HPIPE_INTERFACE_GEN_MAX_MASK);
> -
> - /* Set select Data width 40Bit (SEL_BITS[2:0]) */
> - RegSet (HpipeAddr + HPIPE_LOOPBACK_REG,
> - 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
> -}
> -
> -STATIC
> -VOID
> -ComPhySataSetAnalogParameters (
> - IN EFI_PHYSICAL_ADDRESS HpipeAddr,
> - IN EFI_PHYSICAL_ADDRESS SdIpAddr
> -)
> -{
> - UINT32 Mask, Data;
> -
> - /* Hpipe Generation 1 settings 1 */
> - Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |
> - HPIPE_GX_SET1_RX_SELMUPP_MASK |
> - HPIPE_GX_SET1_RX_SELMUFI_MASK |
> - HPIPE_GX_SET1_RX_SELMUFF_MASK |
> - HPIPE_GX_SET1_RX_DIGCK_DIV_MASK;
> - Data = (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) |
> - (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) |
> - (0x1 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET1_REG, ~Mask, Data);
> -
> - /* Hpipe Generation 1 settings 3 */
> - Mask = HPIPE_GX_SET3_FFE_CAP_SEL_MASK |
> - HPIPE_GX_SET3_FFE_RES_SEL_MASK |
> - HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK |
> - HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK |
> - HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK;
> - Data = 0xf |
> - (0x2 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) |
> - (0x1 << HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET) |
> - (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) |
> - (0x1 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET3_REG, ~Mask, Data);
> -
> - /* Hpipe Generation 2 settings 1 */
> - Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |
> - HPIPE_GX_SET1_RX_SELMUPP_MASK |
> - HPIPE_GX_SET1_RX_SELMUFI_MASK |
> - HPIPE_GX_SET1_RX_SELMUFF_MASK |
> - HPIPE_GX_SET1_RX_DIGCK_DIV_MASK;
> - Data = (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) |
> - (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) |
> - (0x1 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_G2_SET1_REG, ~Mask, Data);
> -
> - /* Hpipe Generation 3 settings 1 */
> - Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |
> - HPIPE_GX_SET1_RX_SELMUPP_MASK |
> - HPIPE_GX_SET1_RX_SELMUFI_MASK |
> - HPIPE_GX_SET1_RX_SELMUFF_MASK |
> - HPIPE_GX_SET1_RX_DFE_EN_MASK |
> - HPIPE_GX_SET1_RX_DIGCK_DIV_MASK |
> - HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_MASK;
> - Data = 0x2 |
> - (0x2 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) |
> - (0x3 << HPIPE_GX_SET1_RX_SELMUFI_OFFSET) |
> - (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) |
> - (0x1 << HPIPE_GX_SET1_RX_DFE_EN_OFFSET) |
> - (0x2 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data);
> -
> - /* DTL Control */
> - Mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK |
> - HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK |
> - HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK |
> - HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK |
> - HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK |
> - HPIPE_PWR_CTR_DTL_CLK_MODE_MASK |
> - HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK;
> - Data = 0x1 |
> - (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) |
> - (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) |
> - (0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) |
> - (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) |
> - (0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) |
> - (0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~Mask, Data);
> -
> - /* Trigger sampler enable pulse (by toggling the bit) */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
> - ~HPIPE_SAMPLER_MASK,
> - 0x1 << HPIPE_SAMPLER_OFFSET
> - );
> - MmioAnd32 (
> - HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
> - ~HPIPE_SAMPLER_MASK
> - );
> -
> - /* VDD Calibration Control 3 */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_VDD_CAL_CTRL_REG,
> - ~HPIPE_EXT_SELLV_RXSAMPL_MASK,
> - 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET
> - );
> -
> - /* DFE Resolution Control */
> - MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK);
> -
> - /* DFE F3-F5 Coefficient Control */
> - MmioAnd32 (
> - HpipeAddr + HPIPE_DFE_F3_F5_REG,
> - ~(HPIPE_DFE_F3_F5_DFE_EN_MASK | HPIPE_DFE_F3_F5_DFE_CTRL_MASK)
> - );
> -
> - /* Hpipe Generation 3 settings 3 */
> - Mask = HPIPE_GX_SET3_FFE_CAP_SEL_MASK |
> - HPIPE_GX_SET3_FFE_RES_SEL_MASK |
> - HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK |
> - HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK |
> - HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK;
> - Data = 0xf |
> - (0x4 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) |
> - (0x1 << HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET) |
> - (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) |
> - (0x3 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET3_REG, ~Mask, Data);
> -
> - /* Hpipe Generation 3 settings 4 */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_G3_SET4_REG,
> - ~HPIPE_GX_SET4_DFE_RES_MASK,
> - 0x2 << HPIPE_GX_SET4_DFE_RES_OFFSET
> - );
> -
> - /* Offset Phase Control - force offset and toggle 'valid' bit */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_PHASE_CONTROL_REG,
> - ~(HPIPE_OS_PH_OFFSET_MASK | HPIPE_OS_PH_OFFSET_FORCE_MASK),
> - 0x5c | (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
> - );
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_PHASE_CONTROL_REG,
> - ~HPIPE_OS_PH_VALID_MASK,
> - 0x1 << HPIPE_OS_PH_VALID_OFFSET
> - );
> - MmioAnd32 (
> - HpipeAddr + HPIPE_PHASE_CONTROL_REG,
> - ~HPIPE_OS_PH_VALID_MASK
> - );
> -
> - /* Set G1 TX amplitude and TX post emphasis value */
> - Mask = HPIPE_GX_SET0_TX_AMP_MASK |
> - HPIPE_GX_SET0_TX_AMP_ADJ_MASK |
> - HPIPE_GX_SET0_TX_EMPH1_MASK |
> - HPIPE_GX_SET0_TX_EMPH1_EN_MASK;
> - Data = (0x8 << HPIPE_GX_SET0_TX_AMP_OFFSET) |
> - (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) |
> - (0x1 << HPIPE_GX_SET0_TX_EMPH1_OFFSET) |
> - (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET0_REG, ~Mask, Data);
> -
> - /* Set G2 TX amplitude and TX post emphasis value */
> - Mask = HPIPE_GX_SET0_TX_AMP_MASK |
> - HPIPE_GX_SET0_TX_AMP_ADJ_MASK |
> - HPIPE_GX_SET0_TX_EMPH1_MASK |
> - HPIPE_GX_SET0_TX_EMPH1_EN_MASK;
> - Data = (0xa << HPIPE_GX_SET0_TX_AMP_OFFSET) |
> - (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) |
> - (0x2 << HPIPE_GX_SET0_TX_EMPH1_OFFSET) |
> - (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_G2_SET0_REG, ~Mask, Data);
> -
> - /* Set G3 TX amplitude and TX post emphasis value */
> - Mask = HPIPE_GX_SET0_TX_AMP_MASK |
> - HPIPE_GX_SET0_TX_AMP_ADJ_MASK |
> - HPIPE_GX_SET0_TX_EMPH1_MASK |
> - HPIPE_GX_SET0_TX_EMPH1_EN_MASK |
> - HPIPE_GX_SET0_TX_SLEW_RATE_SEL_MASK |
> - HPIPE_GX_SET0_TX_SLEW_CTRL_EN_MASK;
> - Data = (0xe << HPIPE_GX_SET0_TX_AMP_OFFSET) |
> - (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) |
> - (0x6 << HPIPE_GX_SET0_TX_EMPH1_OFFSET) |
> - (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET) |
> - (0x4 << HPIPE_GX_SET0_TX_SLEW_RATE_SEL_OFFSET);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET0_REG, ~Mask, Data);
> -
> - /* SERDES External Configuration 2 register - enable spread spectrum clock */
> - MmioOr32 (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK);
> -
> - /* DFE reset sequence */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_PWR_CTR_REG,
> - ~HPIPE_PWR_CTR_RST_DFE_MASK,
> - 0x1
> - );
> - MmioAnd32 (
> - HpipeAddr + HPIPE_PWR_CTR_REG,
> - ~HPIPE_PWR_CTR_RST_DFE_MASK
> - );
> -
> - /* SW reset for interupt logic */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_PWR_CTR_REG,
> - ~HPIPE_PWR_CTR_SFT_RST_MASK,
> - 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET
> - );
> - MmioAnd32 (
> - HpipeAddr + HPIPE_PWR_CTR_REG,
> - ~HPIPE_PWR_CTR_SFT_RST_MASK
> - );
> -}
> -
> -STATIC
> -VOID
> ComPhySataPhyPowerUp (
> IN EFI_PHYSICAL_ADDRESS SataBase
> )
> @@ -1106,30 +842,26 @@ ComPhySataPhyPowerUp (
>
> STATIC
> EFI_STATUS
> -ComPhySataCheckPll (
> - IN EFI_PHYSICAL_ADDRESS HpipeAddr,
> - IN EFI_PHYSICAL_ADDRESS SdIpAddr
> -)
> +ComPhySmc (
> + IN UINT32 FunctionId,
> + EFI_PHYSICAL_ADDRESS ComPhyBaseAddr,
> + IN UINT32 Lane,
> + IN UINT32 Mode
> + )
> {
> - EFI_STATUS Status = EFI_SUCCESS;
> - UINT32 Data,Mask;
> - IN EFI_PHYSICAL_ADDRESS Addr;
> + ARM_SMC_ARGS SmcRegs = {0};
>
> - Addr = SdIpAddr + SD_EXTERNAL_STATUS0_REG;
> - Data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & SD_EXTERNAL_STATUS0_PLL_RX_MASK;
> - Mask = Data;
> - Data = PollingWithTimeout (Addr, Data, Mask, 15000);
> + SmcRegs.Arg0 = FunctionId;
> + SmcRegs.Arg1 = (UINTN)ComPhyBaseAddr;
> + SmcRegs.Arg2 = Lane;
> + SmcRegs.Arg3 = Mode;
> + ArmCallSmc (&SmcRegs);
>
> - if (Data != 0) {
> - DEBUG((DEBUG_INFO, "ComPhy: Read from reg = %p - value = 0x%x\n",
> - HpipeAddr + HPIPE_LANE_STATUS0_REG, Data));
> - DEBUG((DEBUG_ERROR, "ComPhy: SD_EXTERNAL_STATUS0_PLL_TX is %d, SD_EXTERNAL_STATUS0_PLL_RX is %d\n",
> - (Data & SD_EXTERNAL_STATUS0_PLL_TX_MASK),
> - (Data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)));
> - Status = EFI_D_ERROR;
> + if (SmcRegs.Arg0 != 0) {
> + return EFI_DEVICE_ERROR;
> }
>
> - return Status;
> + return EFI_SUCCESS;
> }
>
> STATIC
> @@ -1143,9 +875,6 @@ ComPhySataPowerUp (
> )
> {
> EFI_STATUS Status;
> - EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
> - EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane);
> - EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
>
> DEBUG ((DEBUG_INFO, "ComPhySata: Initialize SATA PHYs\n"));
>
> @@ -1153,123 +882,29 @@ ComPhySataPowerUp (
>
> ComPhySataMacPowerDown (Desc[ChipId].SoC->AhciBaseAddress);
>
> - DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
> -
> - ComPhySataRFUConfiguration (ComPhyAddr, SdIpAddr);
> -
> - DEBUG((DEBUG_INFO, "ComPhy: stage: Comphy configuration\n"));
> -
> - ComPhySataPhyConfiguration (HpipeAddr);
> -
> - DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n"));
> -
> - ComPhySataSetAnalogParameters (HpipeAddr, SdIpAddr);
> -
> - DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n"));
> + Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
> + ComPhyBase,
> + Lane,
> + COMPHY_FW_FORMAT (COMPHY_SATA_MODE,
> + Desc[ChipId].SoC->AhciId,
> + COMPHY_SPEED_DEFAULT));
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
>
> ComPhySataPhyPowerUp (Desc[ChipId].SoC->AhciBaseAddress);
>
> - DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n"));
> -
> - Status = ComPhySataCheckPll (HpipeAddr, SdIpAddr);
> -
> - return Status;
> -}
> -
> -STATIC
> -VOID
> -ComPhySgmiiRFUConfiguration (
> - IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
> - IN EFI_PHYSICAL_ADDRESS SdIpAddr,
> - IN UINT32 SgmiiSpeed
> -)
> -{
> - UINT32 Mask, Data;
> -
> - Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
> - Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
> - Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
> - Data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
> - RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
> -
> - /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
> - Mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
> - Data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
> - Mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
> - Mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
> - if (SgmiiSpeed == COMPHY_SPEED_1_25G) {
> - Data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
> - Data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
> - } else {
> - /* 3.125G */
> - Data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
> - Data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
> + Status = ComPhySmc (MV_SIP_COMPHY_PLL_LOCK,
> + ComPhyBase,
> + Lane,
> + COMPHY_FW_FORMAT (COMPHY_SATA_MODE,
> + Desc[ChipId].SoC->AhciId,
> + COMPHY_SPEED_DEFAULT));
> + if (EFI_ERROR (Status)) {
> + return Status;
> }
> - Mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
> - Data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
> - Mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
> - Data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
> - Mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
> - Data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
> - RegSet (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, Data, Mask);
> -
> - /* Release from hard reset */
> - Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
> - Data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
> - Mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
> - Data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
> - Mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
> - Data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
> - RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask);
> -
> - /* Release from hard reset */
> - Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
> - Data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
> - Mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
> - Data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
> - RegSet (SdIpAddr+ SD_EXTERNAL_CONFIG1_REG, Data, Mask);
>
> - /* Wait 1ms - until band gap and ref clock ready */
> - MicroSecondDelay (1000);
> - MemoryFence ();
> -}
> -
> -STATIC
> -VOID
> -ComPhySgmiiPhyConfiguration (
> - IN EFI_PHYSICAL_ADDRESS HpipeAddr
> -)
> -{
> - UINT32 Mask, Data;
> -
> - /* Set reference clock */
> - Mask = HPIPE_MISC_REFCLK_SEL_MASK;
> - Data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
> - RegSet (HpipeAddr + HPIPE_MISC_REG, Data, Mask);
> -
> - /* Power and PLL Control */
> - Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
> - Data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
> - Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
> - Data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
> - RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
> -
> - /* Loopback register */
> - Mask = HPIPE_LOOPBACK_SEL_MASK;
> - Data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET;
> - RegSet (HpipeAddr + HPIPE_LOOPBACK_REG, Data, Mask);
> -
> - /* Rx control 1 */
> - Mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
> - Data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
> - Mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
> - Data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
> - RegSet (HpipeAddr + HPIPE_RX_CONTROL_1_REG, Data, Mask);
> -
> - /* DTL Control */
> - Mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
> - Data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
> - RegSet (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, Data, Mask);
> + return Status;
> }
>
> STATIC
> @@ -1331,321 +966,6 @@ ComPhyEthCommonRFUPowerUp (
> }
>
> STATIC
> -UINTN
> -ComPhySgmiiPowerUp (
> - IN UINT32 Lane,
> - IN UINT32 SgmiiSpeed,
> - IN EFI_PHYSICAL_ADDRESS HpipeBase,
> - IN EFI_PHYSICAL_ADDRESS ComPhyBase
> - )
> -{
> - EFI_STATUS Status = EFI_SUCCESS;
> - EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
> - EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane);
> - EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
> -
> - DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
> -
> - ComPhySgmiiRFUConfiguration (ComPhyAddr, SdIpAddr, SgmiiSpeed);
> -
> - DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
> -
> - ComPhySgmiiPhyConfiguration (HpipeAddr);
> -
> - /* Set analog paramters from ETP(HW) - for now use the default data */
> - DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n"));
> -
> - RegSet (HpipeAddr + HPIPE_G1_SET0_REG,
> - 0x1 << HPIPE_GX_SET0_TX_EMPH1_OFFSET, HPIPE_GX_SET0_TX_EMPH1_MASK);
> -
> - DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx,Rx\n"));
> -
> - Status = ComPhyEthCommonRFUPowerUp (SdIpAddr);
> -
> - return Status;
> -}
> -
> -STATIC
> -VOID
> -ComPhySfiRFUConfiguration (
> - IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
> - IN EFI_PHYSICAL_ADDRESS SdIpAddr
> -)
> -{
> - UINT32 Mask, Data;
> -
> - MmioAndThenOr32 (
> - ComPhyAddr + COMMON_PHY_CFG1_REG,
> - ~(COMMON_PHY_CFG1_PWR_UP_MASK | COMMON_PHY_CFG1_PIPE_SELECT_MASK),
> - COMMON_PHY_CFG1_PWR_UP_MASK
> - );
> -
> - /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
> - Mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK |
> - SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK |
> - SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK |
> - SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK |
> - SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK |
> - SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
> - Data = (0xe << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) |
> - (0xe << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET);
> - MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, ~Mask, Data);
> -
> - /* Release from hard reset */
> - Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK |
> - SD_EXTERNAL_CONFIG1_RESET_CORE_MASK |
> - SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
> - Data = SD_EXTERNAL_CONFIG1_RESET_IN_MASK |
> - SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
> - MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, ~Mask, Data);
> -
> - /* Wait 1ms - until band gap and ref clock are ready */
> - MicroSecondDelay (1000);
> - MemoryFence ();
> -}
> -
> -STATIC
> -VOID
> -ComPhySfiPhyConfiguration (
> - IN EFI_PHYSICAL_ADDRESS HpipeAddr,
> - IN UINT32 SfiSpeed
> -)
> -{
> - UINT32 Mask, Data;
> -
> - /* Set reference clock */
> - Mask = HPIPE_MISC_ICP_FORCE_MASK | HPIPE_MISC_REFCLK_SEL_MASK;
> - Data = (SfiSpeed == COMPHY_SPEED_5_15625G) ?
> - (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) : (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_MISC_REG, ~Mask, Data);
> -
> - /* Power and PLL Control */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_PWR_PLL_REG,
> - ~(HPIPE_PWR_PLL_REF_FREQ_MASK | HPIPE_PWR_PLL_PHY_MODE_MASK),
> - 0x1 | (0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
> - );
> -
> - /* Loopback register */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_LOOPBACK_REG,
> - ~HPIPE_LOOPBACK_SEL_MASK,
> - 0x1 << HPIPE_LOOPBACK_SEL_OFFSET
> - );
> -
> - /* Rx control 1 */
> - MmioOr32 (
> - HpipeAddr + HPIPE_RX_CONTROL_1_REG,
> - HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK | HPIPE_RX_CONTROL_1_CLK8T_EN_MASK
> - );
> -
> - /* DTL Control */
> - MmioOr32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
> -
> - /* Transmitter/Receiver Speed Divider Force */
> - if (SfiSpeed == COMPHY_SPEED_5_15625G) {
> - Mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK |
> - HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK |
> - HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK |
> - HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK;
> - Data = (1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) |
> - (1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) |
> - (1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) |
> - (1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_SPD_DIV_FORCE_REG, ~Mask, Data);
> - } else {
> - MmioOr32 (HpipeAddr + HPIPE_SPD_DIV_FORCE_REG, HPIPE_TXDIGCK_DIV_FORCE_MASK);
> - }
> -}
> -
> -STATIC
> -VOID
> -ComPhySfiSetAnalogParameters (
> - IN EFI_PHYSICAL_ADDRESS HpipeAddr,
> - IN EFI_PHYSICAL_ADDRESS SdIpAddr,
> - IN UINT32 SfiSpeed
> -)
> -{
> - UINT32 Mask, Data;
> -
> - /* SERDES External Configuration 2 */
> - MmioOr32 (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
> -
> - /* DFE Resolution control */
> - MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK);
> -
> - /* Generation 1 setting_0 */
> - if (SfiSpeed == COMPHY_SPEED_5_15625G) {
> - Mask = HPIPE_GX_SET0_TX_EMPH1_MASK;
> - Data = 0x6 << HPIPE_GX_SET0_TX_EMPH1_OFFSET;
> - } else {
> - Mask = HPIPE_GX_SET0_TX_AMP_MASK | HPIPE_GX_SET0_TX_EMPH1_MASK;
> - Data = (0x1c << HPIPE_GX_SET0_TX_AMP_OFFSET) | (0xe << HPIPE_GX_SET0_TX_EMPH1_OFFSET);
> - }
> - MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET0_REG, ~Mask, Data);
> -
> - /* Generation 1 setting 2 */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_GX_SET2_REG,
> - ~HPIPE_GX_SET2_TX_EMPH0_MASK,
> - HPIPE_GX_SET2_TX_EMPH0_EN_MASK
> - );
> -
> - /* Transmitter Slew Rate Control register */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_TX_REG1_REG,
> - ~(HPIPE_TX_REG1_TX_EMPH_RES_MASK | HPIPE_TX_REG1_SLC_EN_MASK),
> - (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) | (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
> - );
> -
> - /* Impedance Calibration Control register */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_CAL_REG1_REG,
> - ~(HPIPE_CAL_REG_1_EXT_TXIMP_MASK | HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK),
> - (0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) | HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK
> - );
> -
> - /* Generation 1 setting 5 */
> - MmioAnd32 (HpipeAddr + HPIPE_G1_SET5_REG, ~HPIPE_GX_SET5_ICP_MASK);
> -
> - /* Generation 1 setting 1 */
> - if (SfiSpeed == COMPHY_SPEED_5_15625G) {
> - Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK | HPIPE_GX_SET1_RX_SELMUPP_MASK;
> - Data = 0x1 | (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET);
> - } else {
> - Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |
> - HPIPE_GX_SET1_RX_SELMUPP_MASK |
> - HPIPE_GX_SET1_RX_SELMUFI_MASK |
> - HPIPE_GX_SET1_RX_SELMUFF_MASK |
> - HPIPE_GX_SET1_RX_DIGCK_DIV_MASK;
> - Data = 0x2 |
> - (0x2 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) |
> - (0x1 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) |
> - (0x3 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET);
> - }
> - MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET1_REG, ~Mask, Data);
> - MmioOr32 (HpipeAddr + HPIPE_G1_SET1_REG, HPIPE_GX_SET1_RX_DFE_EN_MASK);
> -
> - /* DFE F3-F5 Coefficient Control */
> - MmioAnd32 (
> - HpipeAddr + HPIPE_DFE_F3_F5_REG,
> - ~(HPIPE_DFE_F3_F5_DFE_EN_MASK | HPIPE_DFE_F3_F5_DFE_CTRL_MASK)
> - );
> -
> - /* Configure Generation 1 setting 4 (DFE) */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_G1_SET4_REG,
> - ~HPIPE_GX_SET4_DFE_RES_MASK,
> - 0x1 << HPIPE_GX_SET4_DFE_RES_OFFSET
> - );
> -
> - /* Generation 1 setting 3 */
> - MmioOr32 (HpipeAddr + HPIPE_G1_SET3_REG, HPIPE_GX_SET3_FBCK_SEL_MASK);
> -
> - if (SfiSpeed == COMPHY_SPEED_5_15625G) {
> - /* Force FFE (Feed Forward Equalization) to 5G */
> - Mask = HPIPE_GX_SET3_FFE_CAP_SEL_MASK |
> - HPIPE_GX_SET3_FFE_RES_SEL_MASK |
> - HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK;
> - Data = 0xf | (0x4 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) | HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK;
> - MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET3_REG, ~Mask, Data);
> - }
> -
> - /* Configure RX training timer */
> - MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_5_REG, ~HPIPE_RX_TRAIN_TIMER_MASK, 0x13);
> -
> - /* Enable TX train peak to peak hold */
> - MmioOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_0_REG, HPIPE_TX_TRAIN_P2P_HOLD_MASK);
> -
> - /* Configure TX preset index */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_TX_PRESET_INDEX_REG,
> - ~HPIPE_TX_PRESET_INDEX_MASK,
> - 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET
> - );
> -
> - /* Disable pattern lock lost timeout */
> - MmioAnd32 (HpipeAddr + HPIPE_FRAME_DETECT_CTRL_3_REG, ~HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK);
> -
> - /* Configure TX training pattern and TX training 16bit auto */
> - MmioOr32 (
> - HpipeAddr + HPIPE_TX_TRAIN_REG,
> - HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK | HPIPE_TX_TRAIN_PAT_SEL_MASK
> - );
> -
> - /* Configure training pattern number */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_FRAME_DETECT_CTRL_0_REG,
> - ~HPIPE_TRAIN_PAT_NUM_MASK,
> - 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET
> - );
> -
> - /* Configure differential manchester encoder to ethernet mode */
> - MmioOr32 (HpipeAddr + HPIPE_DME_REG, HPIPE_DME_ETHERNET_MODE_MASK);
> -
> - /* Configure VDD Continuous Calibration */
> - MmioOr32 (HpipeAddr + HPIPE_VDD_CAL_0_REG, HPIPE_CAL_VDD_CONT_MODE_MASK);
> -
> - /* Configure sampler gain */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
> - ~HPIPE_RX_SAMPLER_OS_GAIN_MASK,
> - 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET
> - );
> -
> - /* Trigger sampler enable pulse (by toggling the bit) */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
> - ~HPIPE_SAMPLER_MASK,
> - 0x1 << HPIPE_SAMPLER_OFFSET
> - );
> - MmioAnd32 (
> - HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
> - ~HPIPE_SAMPLER_MASK
> - );
> -
> - /* VDD calibration control */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_VDD_CAL_CTRL_REG,
> - ~HPIPE_EXT_SELLV_RXSAMPL_MASK,
> - 0x1a << HPIPE_EXT_SELLV_RXSAMPL_OFFSET
> - );
> -}
> -
> -STATIC
> -EFI_STATUS
> -ComPhySfiPowerUp (
> - IN UINT32 Lane,
> - IN EFI_PHYSICAL_ADDRESS HpipeBase,
> - IN EFI_PHYSICAL_ADDRESS ComPhyBase,
> - IN UINT32 SfiSpeed
> - )
> -{
> - EFI_STATUS Status;
> - EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
> - EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane);
> - EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
> -
> - DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
> -
> - ComPhySfiRFUConfiguration (ComPhyAddr, SdIpAddr);
> -
> - DEBUG ((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
> -
> - ComPhySfiPhyConfiguration (HpipeAddr, SfiSpeed);
> -
> - DEBUG ((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n"));
> -
> - ComPhySfiSetAnalogParameters (HpipeAddr, SdIpAddr, SfiSpeed);
> -
> - DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx,Rx\n"));
> -
> - Status = ComPhyEthCommonRFUPowerUp (SdIpAddr);
> -
> - return Status;
> -}
> -
> -STATIC
> EFI_STATUS
> ComPhyRxauiRFUConfiguration (
> IN UINT32 Lane,
> @@ -1945,11 +1265,20 @@ ComPhyCp110Init (
> case COMPHY_TYPE_SGMII1:
> case COMPHY_TYPE_SGMII2:
> case COMPHY_TYPE_SGMII3:
> - Status = ComPhySgmiiPowerUp(Lane, PtrComPhyMap->Speed, HpipeBaseAddr,
> - ComPhyBaseAddr);
> + Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
> + PtrChipCfg->ComPhyBaseAddr,
> + Lane,
> + COMPHY_FW_FORMAT (COMPHY_SGMII_MODE,
> + (PtrComPhyMap->Type - COMPHY_TYPE_SGMII0),
> + PtrComPhyMap->Speed));
> break;
> case COMPHY_TYPE_SFI:
> - Status = ComPhySfiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr, PtrComPhyMap->Speed);
> + Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
> + PtrChipCfg->ComPhyBaseAddr,
> + Lane,
> + COMPHY_FW_FORMAT (COMPHY_SFI_MODE,
> + COMPHY_UNIT_ID0,
> + PtrComPhyMap->Speed));
> break;
> case COMPHY_TYPE_RXAUI0:
> case COMPHY_TYPE_RXAUI1:
> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
> index 2ef9af4..b3a8c10 100644
> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
> @@ -42,9 +42,9 @@ CHAR16 * TypeStringTable [] = {L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2",
> L"USB3_DEVICE", L"XAUI0", L"XAUI1", L"XAUI2",
> L"XAUI3", L"RXAUI0", L"RXAUI1", L"SFI"};
>
> -CHAR16 * SpeedStringTable [] = {L"-", L"1.25 Gbps", L"1.5 Gbps", L"2.5 Gbps",
> - L"3.0 Gbps", L"3.125 Gbps", L"5 Gbps", L"5.156 Gbps",
> - L"6 Gbps", L"6.25 Gbps", L"10.31 Gbps"};
> +CHAR16 * SpeedStringTable [] = {L"1.25 Gbps", L"2.5 Gbps", L"3.125 Gbps",
> + L"5 Gbps", L"5.156 Gbps", L"6 Gbps",
> + L"10.31 Gbps"};
>
> CHIP_COMPHY_CONFIG ChipCfgTbl[] = {
> {
> @@ -129,7 +129,11 @@ GetSpeedString (
> )
> {
>
> - if (Speed < 0 || Speed > 10) {
> + if (Speed == COMPHY_SPEED_DEFAULT) {
> + return L"default";
> + }
> +
> + if (Speed < 0 || Speed > COMPHY_SPEED_MAX) {
> return L"invalid";
> }
>
> @@ -266,7 +270,6 @@ MvComPhyInit (
> PtrChipCfg->MapData[Lane].Invert = LaneData[Index].InvFlag[Lane];
>
> if ((PtrChipCfg->MapData[Lane].Speed == COMPHY_SPEED_INVALID) ||
> - (PtrChipCfg->MapData[Lane].Speed == COMPHY_SPEED_ERROR) ||
> (PtrChipCfg->MapData[Lane].Type == COMPHY_TYPE_INVALID)) {
> DEBUG((DEBUG_ERROR, "ComPhy: No valid phy speed or type for lane %d, "
> "setting lane as unconnected\n", Lane + 1));
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [platforms: PATCH 2/6] Marvell/Library: ComPhyLib: Configure PCIE in ARM-TF
2018-07-13 14:09 [platforms: PATCH 0/6] Armada7k8k ComPhy rework Marcin Wojtas
2018-07-13 14:09 ` [platforms: PATCH 1/6] Marvell/Library: ComPhyLib: Configure SATA, SGMII and SFI in ARM-TF Marcin Wojtas
@ 2018-07-13 14:09 ` Marcin Wojtas
2018-07-25 10:01 ` Ard Biesheuvel
2018-07-13 14:09 ` [platforms: PATCH 3/6] Marvell/Library: ComPhyLib: Configure RXAUI " Marcin Wojtas
` (4 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Marcin Wojtas @ 2018-07-13 14:09 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Replace the ComPhy initialization for PCIE with appropriate SMC call,
so the firmware will execute required serdes configuration.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h | 22 -
Silicon/Marvell/Include/Library/SampleAtResetLib.h | 7 -
Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 3 +-
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c | 19 -
Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 491 +-------------------
5 files changed, 8 insertions(+), 534 deletions(-)
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h
index 323399f..e47396d 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h
@@ -44,18 +44,6 @@ SAR - Sample At Reset
#define CP110_SAR_BASE(_CpIndex) (0xf2000000 + (0x2000000 * (_CpIndex)) + 0x400200)
-#define MAX_CP_COUNT 2
-#define MAX_PCIE_CLK_TYPE_COUNT 2
-
-#define CP0_PCIE0_CLK_OFFSET 2
-#define CP0_PCIE1_CLK_OFFSET 3
-#define CP1_PCIE0_CLK_OFFSET 0
-#define CP1_PCIE1_CLK_OFFSET 1
-#define CP0_PCIE0_CLK_MASK (1 << CP0_PCIE0_CLK_OFFSET)
-#define CP0_PCIE1_CLK_MASK (1 << CP0_PCIE1_CLK_OFFSET)
-#define CP1_PCIE0_CLK_MASK (1 << CP1_PCIE0_CLK_OFFSET)
-#define CP1_PCIE1_CLK_MASK (1 << CP1_PCIE1_CLK_OFFSET)
-
typedef enum {
CPU_2000_DDR_1200_RCLK_1200 = 0x0,
CPU_2000_DDR_1050_RCLK_1050 = 0x1,
@@ -97,13 +85,3 @@ STATIC CONST PLL_FREQUENCY_DESCRIPTION PllFrequencyTable[SAR_MAX_OPTIONS] = {
{800 , 800 , 800 , CPU_800_DDR_800_RCLK_800},
{1000, 800 , 800 , CPU_1000_DDR_800_RCLK_800}
};
-
-STATIC CONST UINT32 PcieClockMask[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT] = {
- {CP0_PCIE0_CLK_MASK, CP0_PCIE1_CLK_MASK},
- {CP1_PCIE0_CLK_MASK, CP1_PCIE1_CLK_MASK}
-};
-
-STATIC CONST UINT32 PcieClockOffset[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT] = {
- {CP0_PCIE0_CLK_OFFSET, CP0_PCIE1_CLK_OFFSET},
- {CP1_PCIE0_CLK_OFFSET, CP1_PCIE1_CLK_OFFSET}
-};
diff --git a/Silicon/Marvell/Include/Library/SampleAtResetLib.h b/Silicon/Marvell/Include/Library/SampleAtResetLib.h
index 1be3a6a..1e7b27c 100644
--- a/Silicon/Marvell/Include/Library/SampleAtResetLib.h
+++ b/Silicon/Marvell/Include/Library/SampleAtResetLib.h
@@ -47,11 +47,4 @@ SampleAtResetGetDramFrequency (
VOID
);
-UINT32
-EFIAPI
-SampleAtResetGetPcieClockDirection (
- IN UINT32 CpIndex,
- IN UINT32 PcieIndex
- );
-
#endif /* __SAMPLE_AT_RESET_LIB_H__ */
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
index 34c1e9b..20a9767 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
@@ -125,7 +125,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define COMPHY_FW_FORMAT(mode, idx, speeds) \
((mode << 12) | (idx << 8) | (speeds << 2))
-
+#define COMPHY_FW_PCIE_FORMAT(pcie_width, mode, speeds) \
+ ((pcie_width << 18) | COMPHY_FW_FORMAT (mode, 0, speeds))
#define COMPHY_POLARITY_NO_INVERT 0
#define COMPHY_POLARITY_TXD_INVERT 1
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c
index 3ebff56..5a9a5f9 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c
@@ -90,22 +90,3 @@ SampleAtResetGetDramFrequency (
return PllFrequencies->DdrFrequency;
}
-
-UINT32
-EFIAPI
-SampleAtResetGetPcieClockDirection (
- IN UINT32 CpIndex,
- IN UINT32 PcieIndex
- )
-{
- UINT32 ClockDirection;
-
- ASSERT (CpIndex < MAX_CP_COUNT);
- ASSERT (PcieIndex < MAX_PCIE_CLK_TYPE_COUNT);
-
- ClockDirection = MmioAnd32 (CP110_SAR_BASE (CpIndex),
- PcieClockMask[CpIndex][PcieIndex] >>
- PcieClockOffset[CpIndex][PcieIndex]);
-
- return ClockDirection;
-}
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
index 4b8b27a..6cefee9 100755
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
@@ -46,9 +46,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define HPIPE_ADDR(base, Lane) (SD_ADDR(base, Lane) + HPIPE_ADDR_OFFSET)
#define COMPHY_ADDR(base, Lane) (base + COMPHY_ADDR_LANE_WIDTH * Lane)
-#define CP110_PCIE_REF_CLK_TYPE0 0
-#define CP110_PCIE_REF_CLK_TYPE12 1
-
/*
* For CP-110 we have 2 Selector registers "PHY Selectors"
* and " PIPE Selectors".
@@ -103,487 +100,6 @@ COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {
STATIC
VOID
-ComPhyPcieRFUConfiguration (
- IN UINT32 Lane,
- IN UINT32 PcieWidth,
- IN EFI_PHYSICAL_ADDRESS ComPhyAddr
-)
-{
- UINT32 Mask, Data;
-
- /* Enable PCIe by4 and by2 */
- if (Lane == 0) {
- if (PcieWidth == 4) {
- RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
- COMMON_PHY_SD_CTRL1_PCIE_X4_EN,
- COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK);
- } else if (PcieWidth == 2) {
- RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
- COMMON_PHY_SD_CTRL1_PCIE_X2_EN,
- COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK);
- }
- }
-
- /* RFU configurations - hard reset ComPhy */
- Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
- Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
- Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
- Data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
- Mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
- Data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
- Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
- Data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
- Mask |= COMMON_PHY_PHY_MODE_MASK;
- Data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET;
- RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
-
- /* Release from hard reset */
- Mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
- Data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
- Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
- Data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
- RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
-
- /* Wait 1ms - until band gap and ref clock ready */
- MicroSecondDelay (1000);
- MemoryFence ();
-}
-
-STATIC
-VOID
-ComPhyPciePhyConfiguration (
- IN UINT32 Lane,
- IN UINT32 PcieWidth,
- IN UINT32 PcieClk,
- IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
- IN EFI_PHYSICAL_ADDRESS HpipeAddr
-)
-{
- UINT32 Mask, Data;
-
- /* Set PIPE soft reset */
- Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
- Data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
-
- /* Set PHY Datapath width mode for V0 */
- Mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
- Data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
-
- /* Set Data bus width USB mode for V0 */
- Mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
- Data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
-
- /* Set CORE_CLK output frequency for 250Mhz */
- Mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
- Data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
- RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask);
-
- /* Set PLL ready delay for 0x2 */
- Data = HPIPE_CLK_SRC_LO_PLL_RDY_DL_DEFAULT;
- Mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
- if (PcieWidth != 1) {
- Data |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_DEFAULT |
- HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_DEFAULT;
- Mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK |
- HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
- }
- RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, Data, Mask);
-
- /* Set PIPE mode interface to PCIe3 - 0x1 */
- Data = HPIPE_CLK_SRC_HI_MODE_PIPE_EN;
- Mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
- if (PcieWidth != 1) {
- Mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK |
- HPIPE_CLK_SRC_HI_LANE_MASTER_MASK |
- HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
- if (Lane == 0) {
- Data |= HPIPE_CLK_SRC_HI_LANE_STRT_EN |
- HPIPE_CLK_SRC_HI_LANE_MASTER_EN;
- } else if (Lane == (PcieWidth - 1)) {
- Data |= HPIPE_CLK_SRC_HI_LANE_BREAK_EN;
- }
- }
- RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, Data, Mask);
-
- /* Config update polarity equalization */
- RegSet (HpipeAddr + HPIPE_LANE_EQ_CFG1_REG,
- 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET, HPIPE_CFG_UPDATE_POLARITY_MASK);
-
- /* Set PIPE version 4 to mode enable */
- RegSet (HpipeAddr + HPIPE_DFE_CTRL_28_REG,
- 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, HPIPE_DFE_CTRL_28_PIPE4_MASK);
-
- /* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz clock */
- Mask = HPIPE_MISC_TXDCLK_2X_MASK;
- Data = HPIPE_MISC_TXDCLK_2X_500MHZ;
-
- /* Enable 500MHz Clock */
- Mask |= HPIPE_MISC_CLK500_EN_MASK;
- Data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
-
- if (PcieClk) {
- /*
- * Enable PIN clock 100M_125M
- * Only if clock is output, configure the clock-source mux
- */
- Mask |= HPIPE_MISC_CLK100M_125M_MASK;
- Data |= HPIPE_MISC_CLK100M_125M_EN;
- /* Set reference clock comes from group 1 */
- Mask |= HPIPE_MISC_REFCLK_SEL_MASK;
- Data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
- } else {
- /* Set reference clock comes from group 2 */
- Mask |= HPIPE_MISC_REFCLK_SEL_MASK;
- Data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
- }
-
- /* Force ICP */
- Mask |= HPIPE_MISC_ICP_FORCE_MASK;
- Data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
- RegSet (HpipeAddr + HPIPE_MISC_REG, Data, Mask);
-
- if (PcieClk) {
- /* Set reference frequcency select - 0x2 for 25MHz*/
- Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
- Data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
- } else {
- /* Set reference frequcency select - 0x0 for 100MHz*/
- Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
- Data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
- }
-
- /* Set PHY mode to PCIe */
- Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
- Data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
- RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
-
- /* Ref clock alignment */
- if (PcieWidth != 1) {
- RegSet (HpipeAddr + HPIPE_LANE_ALIGN_REG,
- HPIPE_LANE_ALIGN_OFF,
- HPIPE_LANE_ALIGN_OFF_MASK);
- }
-
- /*
- * Set the amount of time spent in the LoZ state - set
- * for 0x7 only if the PCIe clock is output
- */
- if (PcieClk)
- RegSet (HpipeAddr + HPIPE_GLOBAL_PM_CTRL,
- 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
- HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
-
- /* Set Maximal PHY Generation Setting (8Gbps) */
- Mask = HPIPE_INTERFACE_GEN_MAX_MASK;
- Data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
- /* Bypass frame detection and sync detection for RX DATA */
- Mask |= HPIPE_INTERFACE_DET_BYPASS_MASK;
- Data |= 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET;
- /* Set Link Train Mode (Tx training control pins are used) */
- Mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
- Data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
- RegSet (HpipeAddr + HPIPE_INTERFACE_REG, Data, Mask);
-
- /* Set Idle_sync enable */
- Mask = HPIPE_PCIE_IDLE_SYNC_MASK;
- Data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET;
-
- /* Select bits for PCIE Gen3(32bit) */
- Mask |= HPIPE_PCIE_SEL_BITS_MASK;
- Data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET;
- RegSet (HpipeAddr + HPIPE_PCIE_REG0, Data, Mask);
-
- /* Enable Tx_adapt_g1 */
- Mask = HPIPE_TX_TRAIN_CTRL_G1_MASK;
- Data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET;
-
- /* Enable Tx_adapt_gn1 */
- Mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK;
- Data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET;
-
- /* Disable Tx_adapt_g0 */
- Mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK;
- Data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
- RegSet (HpipeAddr + HPIPE_TX_TRAIN_CTRL_REG, Data, Mask);
-
- /* Set reg_tx_train_chk_init */
- Mask = HPIPE_TX_TRAIN_CHK_INIT_MASK;
- Data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET;
-
- /* Enable TX_COE_FM_PIN_PCIE3_EN */
- Mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK;
- Data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET;
- RegSet (HpipeAddr + HPIPE_TX_TRAIN_REG, Data, Mask);
-}
-
-STATIC
-VOID
-ComPhyPcieSetAnalogParameters (
- IN EFI_PHYSICAL_ADDRESS HpipeAddr
-)
-{
- UINT32 Data, Mask;
-
- /* Set preset sweep configurations */
- Mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK |
- HPIPE_TX_NUM_OF_PRESET_MASK |
- HPIPE_TX_SWEEP_PRESET_EN_MASK;
- Data = (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) |
- (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) |
- (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_11_REG, ~Mask, Data);
-
- /* Tx train start configuration */
- Mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK |
- HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK |
- HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK |
- HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK;
- Data = (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) |
- (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_5_REG, ~Mask, Data);
-
- /* Enable Tx train P2P */
- MmioOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_0_REG, HPIPE_TX_TRAIN_P2P_HOLD_MASK);
-
- /* Configure Tx train timeout */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_TX_TRAIN_CTRL_4_REG,
- ~HPIPE_TRX_TRAIN_TIMER_MASK,
- 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET
- );
-
- /* Disable G0/G1/GN1 adaptation */
- MmioAnd32 (
- HpipeAddr + HPIPE_TX_TRAIN_CTRL_REG,
- ~(HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK | HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
- );
-
- /* Disable DTL frequency loop */
- MmioAnd32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
-
- /* Configure Generation 3 DFE */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_G3_SET4_REG,
- ~HPIPE_GX_SET4_DFE_RES_MASK,
- 0x3 << HPIPE_GX_SET4_DFE_RES_OFFSET
- );
-
- /* Use TX/RX training result for DFE */
- MmioAnd32 (HpipeAddr + HPIPE_DFE_REG0, ~HPIPE_DFE_RES_FORCE_MASK);
-
- /* Configure initial and final coefficient value for receiver */
- MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data);
- Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |
- HPIPE_GX_SET1_RX_SELMUPP_MASK |
- HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_MASK;
- Data = 0x1 | (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data);
-
- /* Trigger sampler 5us enable pulse */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
- ~HPIPE_SAMPLER_MASK,
- 0x1 << HPIPE_SAMPLER_OFFSET
- );
- MicroSecondDelay (5);
- MmioAnd32 (
- HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
- ~HPIPE_SAMPLER_MASK
- );
-
- /* FFE resistor tuning for different bandwidth */
- Mask = HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK |
- HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK;
- Data = (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) |
- (0x3 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET3_REG, ~Mask, Data);
-
- /* Pattern lock lost timeout disable */
- MmioAnd32 (HpipeAddr + HPIPE_FRAME_DETECT_CTRL_3_REG, ~HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK);
-
- /* Configure DFE adaptations */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_CDR_CONTROL_REG,
- ~(HPIPE_CDR_MAX_DFE_ADAPT_1_MASK | HPIPE_CDR_MAX_DFE_ADAPT_0_MASK | HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK),
- 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET
- );
- MmioAnd32 (HpipeAddr + HPIPE_DFE_CONTROL_REG, ~HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK);
-
- /* Hpipe Generation 2 setting 1*/
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_G2_SET1_REG,
- ~(HPIPE_GX_SET1_RX_SELMUPI_MASK | HPIPE_GX_SET1_RX_SELMUPP_MASK | HPIPE_GX_SET1_RX_SELMUFI_MASK),
- 0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET
- );
-
- /* DFE enable */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_G2_SET4_REG,
- ~HPIPE_GX_SET4_DFE_RES_MASK,
- 0x3 << HPIPE_GX_SET4_DFE_RES_OFFSET
- );
-
- /* Configure DFE Resolution */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_LANE_CFG4_REG,
- ~HPIPE_LANE_CFG4_DFE_EN_SEL_MASK,
- 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET
- );
-
- /* VDD calibration control */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_VDD_CAL_CTRL_REG,
- ~HPIPE_EXT_SELLV_RXSAMPL_MASK,
- 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET
- );
-
- /* Set PLL Charge-pump Current Control */
- MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET5_REG, ~HPIPE_GX_SET5_ICP_MASK, 0x4);
-
- /* Set lane rqualization remote setting */
- Mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK |
- HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK |
- HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
- Data = (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) |
- (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) |
- (HPIPE_LANE_CFG_FOM_PRESET_VECTOR_DEFAULT);
- MmioAndThenOr32 (HpipeAddr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, ~Mask, Data);
-
- /* Set phy in root complex mode */
- MmioOr32 (HpipeAddr + HPIPE_LANE_EQU_CONFIG_0_REG, HPIPE_CFG_PHY_RC_EP_MASK);
-}
-
-STATIC
-EFI_STATUS
-ComPhyPciePhyPowerUp (
- IN UINT32 Lane,
- IN UINT32 PcieWidth,
- IN EFI_PHYSICAL_ADDRESS ComPhyBase,
- IN EFI_PHYSICAL_ADDRESS HpipeBase
-)
-{
- EFI_STATUS Status = EFI_SUCCESS;
- UINT8 StartLane, EndLane, Loop;
- UINT32 Data;
-
- /*
- * For PCIe by4 or by2 - release from reset only after finish to
- * configure all lanes
- */
- if ((PcieWidth == 1) || (Lane == (PcieWidth - 1))) {
- if (PcieWidth != 1) {
- /* Allows writing to all lanes in one write */
- RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
- COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_ENABLE,
- COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
- StartLane = 0;
- EndLane = PcieWidth;
-
- /*
- * Release from PIPE soft reset
- * for PCIe by4 or by2 - release from soft reset
- * all lanes - can't use read modify write
- */
- RegSet (HPIPE_ADDR (HpipeBase, 0) + HPIPE_RST_CLK_CTRL_REG,
- HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 | HPIPE_RST_CLK_CTRL_MODE_REFDIV_4,
- HPIPE_RST_CLK_CTRL_CLR_ALL_MASK);
- } else {
- StartLane = Lane;
- EndLane = Lane + 1;
-
- /*
- * Release from PIPE soft reset
- * for PCIe by4 or by2 - release from soft reset
- * all lanes
- */
- RegSet (HPIPE_ADDR (HpipeBase, Lane) + HPIPE_RST_CLK_CTRL_REG,
- HPIPE_RST_CLK_CTRL_PIPE_RST_DISABLE,
- HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
- }
-
- if (PcieWidth != 1) {
- /* Disable writing to all lanes with one write */
- RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
- COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_DISABLE,
- COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
- }
- MemoryFence ();
-
- /* Wait 20ms until status of all lanes stabilize */
- MicroSecondDelay (20000);
-
- /* Make sure all lanes are UP */
- for (Loop = StartLane; Loop < EndLane; Loop++) {
- Data = MmioRead32 (HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG);
-
- if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) {
- DEBUG ((DEBUG_ERROR,
- "%a: Read from lane%d, reg = %p - value = 0x%x\n",
- __FUNCTION__,
- Loop,
- HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG,
- Data));
- DEBUG ((DEBUG_ERROR,
- "%a: HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n",
- __FUNCTION__));
- Status = EFI_D_ERROR;
- break;
- }
- }
- }
-
- return Status;
-}
-
-STATIC
-EFI_STATUS
-ComPhyPciePowerUp (
- IN UINT8 ChipId,
- IN UINT32 Lane,
- IN UINT32 PcieWidth,
- IN EFI_PHYSICAL_ADDRESS HpipeBase,
- IN EFI_PHYSICAL_ADDRESS ComPhyBase
- )
-{
- EFI_STATUS Status = EFI_SUCCESS;
- EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
- EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
- UINT32 PcieClk;
-
- /*
- * Obtain clock direction from sample-at-reset configuration.
- * 4th and 5th SerDes lanes can belong only to PCIE Port1 and
- * Port2, which use different clock type specifier than Port0.
- */
- if (Lane == 4 || Lane == 5) {
- PcieClk = SampleAtResetGetPcieClockDirection (ChipId, CP110_PCIE_REF_CLK_TYPE12);
- } else {
- PcieClk = SampleAtResetGetPcieClockDirection (ChipId, CP110_PCIE_REF_CLK_TYPE0);
- }
-
- DEBUG ((DEBUG_INFO, "%a: ChipId: %d PcieClk:%d\n", __FUNCTION__, ChipId, PcieClk));
-
- DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
-
- ComPhyPcieRFUConfiguration (Lane, PcieWidth, ComPhyAddr);
-
- DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
-
- ComPhyPciePhyConfiguration (Lane, PcieWidth, PcieClk, ComPhyAddr, HpipeAddr);
-
- DEBUG((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n"));
-
- ComPhyPcieSetAnalogParameters (HpipeAddr);
-
- DEBUG ((DEBUG_INFO, "%a: stage: ComPhy power up and check PLL\n", __FUNCTION__));
-
- Status = ComPhyPciePhyPowerUp (Lane, PcieWidth, ComPhyBase, HpipeBase);
-
- return Status;
-}
-
-STATIC
-VOID
ComPhyUsb3RFUConfiguration (
IN EFI_PHYSICAL_ADDRESS ComPhyAddr
)
@@ -1229,7 +745,12 @@ ComPhyCp110Init (
case COMPHY_TYPE_PCIE1:
case COMPHY_TYPE_PCIE2:
case COMPHY_TYPE_PCIE3:
- Status = ComPhyPciePowerUp (ChipId, Lane, PcieWidth, HpipeBaseAddr, ComPhyBaseAddr);
+ Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
+ PtrChipCfg->ComPhyBaseAddr,
+ Lane,
+ COMPHY_FW_PCIE_FORMAT (PcieWidth,
+ COMPHY_PCIE_MODE,
+ PtrComPhyMap->Speed));
break;
case COMPHY_TYPE_SATA0:
case COMPHY_TYPE_SATA1:
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [platforms: PATCH 2/6] Marvell/Library: ComPhyLib: Configure PCIE in ARM-TF
2018-07-13 14:09 ` [platforms: PATCH 2/6] Marvell/Library: ComPhyLib: Configure PCIE " Marcin Wojtas
@ 2018-07-25 10:01 ` Ard Biesheuvel
2018-07-25 10:32 ` Marcin Wojtas
0 siblings, 1 reply; 11+ messages in thread
From: Ard Biesheuvel @ 2018-07-25 10:01 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel@lists.01.org, Leif Lindholm, Nadav Haklai,
Jan Dąbroś, Grzegorz Jaszczyk
On 13 July 2018 at 16:09, Marcin Wojtas <mw@semihalf.com> wrote:
> From: Grzegorz Jaszczyk <jaz@semihalf.com>
>
> Replace the ComPhy initialization for PCIE with appropriate SMC call,
> so the firmware will execute required serdes configuration.
>
'the firmware' ?
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h | 22 -
> Silicon/Marvell/Include/Library/SampleAtResetLib.h | 7 -
> Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 3 +-
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c | 19 -
> Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 491 +-------------------
> 5 files changed, 8 insertions(+), 534 deletions(-)
>
> diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h
> index 323399f..e47396d 100644
> --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h
> +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h
> @@ -44,18 +44,6 @@ SAR - Sample At Reset
>
> #define CP110_SAR_BASE(_CpIndex) (0xf2000000 + (0x2000000 * (_CpIndex)) + 0x400200)
>
> -#define MAX_CP_COUNT 2
> -#define MAX_PCIE_CLK_TYPE_COUNT 2
> -
> -#define CP0_PCIE0_CLK_OFFSET 2
> -#define CP0_PCIE1_CLK_OFFSET 3
> -#define CP1_PCIE0_CLK_OFFSET 0
> -#define CP1_PCIE1_CLK_OFFSET 1
> -#define CP0_PCIE0_CLK_MASK (1 << CP0_PCIE0_CLK_OFFSET)
> -#define CP0_PCIE1_CLK_MASK (1 << CP0_PCIE1_CLK_OFFSET)
> -#define CP1_PCIE0_CLK_MASK (1 << CP1_PCIE0_CLK_OFFSET)
> -#define CP1_PCIE1_CLK_MASK (1 << CP1_PCIE1_CLK_OFFSET)
> -
> typedef enum {
> CPU_2000_DDR_1200_RCLK_1200 = 0x0,
> CPU_2000_DDR_1050_RCLK_1050 = 0x1,
> @@ -97,13 +85,3 @@ STATIC CONST PLL_FREQUENCY_DESCRIPTION PllFrequencyTable[SAR_MAX_OPTIONS] = {
> {800 , 800 , 800 , CPU_800_DDR_800_RCLK_800},
> {1000, 800 , 800 , CPU_1000_DDR_800_RCLK_800}
> };
> -
> -STATIC CONST UINT32 PcieClockMask[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT] = {
> - {CP0_PCIE0_CLK_MASK, CP0_PCIE1_CLK_MASK},
> - {CP1_PCIE0_CLK_MASK, CP1_PCIE1_CLK_MASK}
> -};
> -
> -STATIC CONST UINT32 PcieClockOffset[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT] = {
> - {CP0_PCIE0_CLK_OFFSET, CP0_PCIE1_CLK_OFFSET},
> - {CP1_PCIE0_CLK_OFFSET, CP1_PCIE1_CLK_OFFSET}
> -};
> diff --git a/Silicon/Marvell/Include/Library/SampleAtResetLib.h b/Silicon/Marvell/Include/Library/SampleAtResetLib.h
> index 1be3a6a..1e7b27c 100644
> --- a/Silicon/Marvell/Include/Library/SampleAtResetLib.h
> +++ b/Silicon/Marvell/Include/Library/SampleAtResetLib.h
> @@ -47,11 +47,4 @@ SampleAtResetGetDramFrequency (
> VOID
> );
>
> -UINT32
> -EFIAPI
> -SampleAtResetGetPcieClockDirection (
> - IN UINT32 CpIndex,
> - IN UINT32 PcieIndex
> - );
> -
> #endif /* __SAMPLE_AT_RESET_LIB_H__ */
> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> index 34c1e9b..20a9767 100644
> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
> @@ -125,7 +125,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>
> #define COMPHY_FW_FORMAT(mode, idx, speeds) \
> ((mode << 12) | (idx << 8) | (speeds << 2))
> -
> +#define COMPHY_FW_PCIE_FORMAT(pcie_width, mode, speeds) \
> + ((pcie_width << 18) | COMPHY_FW_FORMAT (mode, 0, speeds))
>
> #define COMPHY_POLARITY_NO_INVERT 0
> #define COMPHY_POLARITY_TXD_INVERT 1
> diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c
> index 3ebff56..5a9a5f9 100644
> --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c
> +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c
> @@ -90,22 +90,3 @@ SampleAtResetGetDramFrequency (
>
> return PllFrequencies->DdrFrequency;
> }
> -
> -UINT32
> -EFIAPI
> -SampleAtResetGetPcieClockDirection (
> - IN UINT32 CpIndex,
> - IN UINT32 PcieIndex
> - )
> -{
> - UINT32 ClockDirection;
> -
> - ASSERT (CpIndex < MAX_CP_COUNT);
> - ASSERT (PcieIndex < MAX_PCIE_CLK_TYPE_COUNT);
> -
> - ClockDirection = MmioAnd32 (CP110_SAR_BASE (CpIndex),
> - PcieClockMask[CpIndex][PcieIndex] >>
> - PcieClockOffset[CpIndex][PcieIndex]);
> -
> - return ClockDirection;
> -}
> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> index 4b8b27a..6cefee9 100755
> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
> @@ -46,9 +46,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> #define HPIPE_ADDR(base, Lane) (SD_ADDR(base, Lane) + HPIPE_ADDR_OFFSET)
> #define COMPHY_ADDR(base, Lane) (base + COMPHY_ADDR_LANE_WIDTH * Lane)
>
> -#define CP110_PCIE_REF_CLK_TYPE0 0
> -#define CP110_PCIE_REF_CLK_TYPE12 1
> -
> /*
> * For CP-110 we have 2 Selector registers "PHY Selectors"
> * and " PIPE Selectors".
> @@ -103,487 +100,6 @@ COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {
>
> STATIC
> VOID
> -ComPhyPcieRFUConfiguration (
> - IN UINT32 Lane,
> - IN UINT32 PcieWidth,
> - IN EFI_PHYSICAL_ADDRESS ComPhyAddr
> -)
> -{
> - UINT32 Mask, Data;
> -
> - /* Enable PCIe by4 and by2 */
> - if (Lane == 0) {
> - if (PcieWidth == 4) {
> - RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
> - COMMON_PHY_SD_CTRL1_PCIE_X4_EN,
> - COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK);
> - } else if (PcieWidth == 2) {
> - RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
> - COMMON_PHY_SD_CTRL1_PCIE_X2_EN,
> - COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK);
> - }
> - }
> -
> - /* RFU configurations - hard reset ComPhy */
> - Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
> - Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
> - Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
> - Data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
> - Mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
> - Data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
> - Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
> - Data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
> - Mask |= COMMON_PHY_PHY_MODE_MASK;
> - Data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET;
> - RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
> -
> - /* Release from hard reset */
> - Mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
> - Data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
> - Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
> - Data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
> - RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
> -
> - /* Wait 1ms - until band gap and ref clock ready */
> - MicroSecondDelay (1000);
> - MemoryFence ();
> -}
> -
> -STATIC
> -VOID
> -ComPhyPciePhyConfiguration (
> - IN UINT32 Lane,
> - IN UINT32 PcieWidth,
> - IN UINT32 PcieClk,
> - IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
> - IN EFI_PHYSICAL_ADDRESS HpipeAddr
> -)
> -{
> - UINT32 Mask, Data;
> -
> - /* Set PIPE soft reset */
> - Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
> - Data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
> -
> - /* Set PHY Datapath width mode for V0 */
> - Mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
> - Data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
> -
> - /* Set Data bus width USB mode for V0 */
> - Mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
> - Data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
> -
> - /* Set CORE_CLK output frequency for 250Mhz */
> - Mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
> - Data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
> - RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask);
> -
> - /* Set PLL ready delay for 0x2 */
> - Data = HPIPE_CLK_SRC_LO_PLL_RDY_DL_DEFAULT;
> - Mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
> - if (PcieWidth != 1) {
> - Data |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_DEFAULT |
> - HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_DEFAULT;
> - Mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK |
> - HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
> - }
> - RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, Data, Mask);
> -
> - /* Set PIPE mode interface to PCIe3 - 0x1 */
> - Data = HPIPE_CLK_SRC_HI_MODE_PIPE_EN;
> - Mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
> - if (PcieWidth != 1) {
> - Mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK |
> - HPIPE_CLK_SRC_HI_LANE_MASTER_MASK |
> - HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
> - if (Lane == 0) {
> - Data |= HPIPE_CLK_SRC_HI_LANE_STRT_EN |
> - HPIPE_CLK_SRC_HI_LANE_MASTER_EN;
> - } else if (Lane == (PcieWidth - 1)) {
> - Data |= HPIPE_CLK_SRC_HI_LANE_BREAK_EN;
> - }
> - }
> - RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, Data, Mask);
> -
> - /* Config update polarity equalization */
> - RegSet (HpipeAddr + HPIPE_LANE_EQ_CFG1_REG,
> - 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET, HPIPE_CFG_UPDATE_POLARITY_MASK);
> -
> - /* Set PIPE version 4 to mode enable */
> - RegSet (HpipeAddr + HPIPE_DFE_CTRL_28_REG,
> - 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, HPIPE_DFE_CTRL_28_PIPE4_MASK);
> -
> - /* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz clock */
> - Mask = HPIPE_MISC_TXDCLK_2X_MASK;
> - Data = HPIPE_MISC_TXDCLK_2X_500MHZ;
> -
> - /* Enable 500MHz Clock */
> - Mask |= HPIPE_MISC_CLK500_EN_MASK;
> - Data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
> -
> - if (PcieClk) {
> - /*
> - * Enable PIN clock 100M_125M
> - * Only if clock is output, configure the clock-source mux
> - */
> - Mask |= HPIPE_MISC_CLK100M_125M_MASK;
> - Data |= HPIPE_MISC_CLK100M_125M_EN;
> - /* Set reference clock comes from group 1 */
> - Mask |= HPIPE_MISC_REFCLK_SEL_MASK;
> - Data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
> - } else {
> - /* Set reference clock comes from group 2 */
> - Mask |= HPIPE_MISC_REFCLK_SEL_MASK;
> - Data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
> - }
> -
> - /* Force ICP */
> - Mask |= HPIPE_MISC_ICP_FORCE_MASK;
> - Data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
> - RegSet (HpipeAddr + HPIPE_MISC_REG, Data, Mask);
> -
> - if (PcieClk) {
> - /* Set reference frequcency select - 0x2 for 25MHz*/
> - Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
> - Data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
> - } else {
> - /* Set reference frequcency select - 0x0 for 100MHz*/
> - Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
> - Data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
> - }
> -
> - /* Set PHY mode to PCIe */
> - Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
> - Data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
> - RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
> -
> - /* Ref clock alignment */
> - if (PcieWidth != 1) {
> - RegSet (HpipeAddr + HPIPE_LANE_ALIGN_REG,
> - HPIPE_LANE_ALIGN_OFF,
> - HPIPE_LANE_ALIGN_OFF_MASK);
> - }
> -
> - /*
> - * Set the amount of time spent in the LoZ state - set
> - * for 0x7 only if the PCIe clock is output
> - */
> - if (PcieClk)
> - RegSet (HpipeAddr + HPIPE_GLOBAL_PM_CTRL,
> - 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
> - HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
> -
> - /* Set Maximal PHY Generation Setting (8Gbps) */
> - Mask = HPIPE_INTERFACE_GEN_MAX_MASK;
> - Data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
> - /* Bypass frame detection and sync detection for RX DATA */
> - Mask |= HPIPE_INTERFACE_DET_BYPASS_MASK;
> - Data |= 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET;
> - /* Set Link Train Mode (Tx training control pins are used) */
> - Mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
> - Data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
> - RegSet (HpipeAddr + HPIPE_INTERFACE_REG, Data, Mask);
> -
> - /* Set Idle_sync enable */
> - Mask = HPIPE_PCIE_IDLE_SYNC_MASK;
> - Data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET;
> -
> - /* Select bits for PCIE Gen3(32bit) */
> - Mask |= HPIPE_PCIE_SEL_BITS_MASK;
> - Data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET;
> - RegSet (HpipeAddr + HPIPE_PCIE_REG0, Data, Mask);
> -
> - /* Enable Tx_adapt_g1 */
> - Mask = HPIPE_TX_TRAIN_CTRL_G1_MASK;
> - Data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET;
> -
> - /* Enable Tx_adapt_gn1 */
> - Mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK;
> - Data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET;
> -
> - /* Disable Tx_adapt_g0 */
> - Mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK;
> - Data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
> - RegSet (HpipeAddr + HPIPE_TX_TRAIN_CTRL_REG, Data, Mask);
> -
> - /* Set reg_tx_train_chk_init */
> - Mask = HPIPE_TX_TRAIN_CHK_INIT_MASK;
> - Data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET;
> -
> - /* Enable TX_COE_FM_PIN_PCIE3_EN */
> - Mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK;
> - Data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET;
> - RegSet (HpipeAddr + HPIPE_TX_TRAIN_REG, Data, Mask);
> -}
> -
> -STATIC
> -VOID
> -ComPhyPcieSetAnalogParameters (
> - IN EFI_PHYSICAL_ADDRESS HpipeAddr
> -)
> -{
> - UINT32 Data, Mask;
> -
> - /* Set preset sweep configurations */
> - Mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK |
> - HPIPE_TX_NUM_OF_PRESET_MASK |
> - HPIPE_TX_SWEEP_PRESET_EN_MASK;
> - Data = (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) |
> - (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) |
> - (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_11_REG, ~Mask, Data);
> -
> - /* Tx train start configuration */
> - Mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK |
> - HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK |
> - HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK |
> - HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK;
> - Data = (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) |
> - (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_5_REG, ~Mask, Data);
> -
> - /* Enable Tx train P2P */
> - MmioOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_0_REG, HPIPE_TX_TRAIN_P2P_HOLD_MASK);
> -
> - /* Configure Tx train timeout */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_TX_TRAIN_CTRL_4_REG,
> - ~HPIPE_TRX_TRAIN_TIMER_MASK,
> - 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET
> - );
> -
> - /* Disable G0/G1/GN1 adaptation */
> - MmioAnd32 (
> - HpipeAddr + HPIPE_TX_TRAIN_CTRL_REG,
> - ~(HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK | HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
> - );
> -
> - /* Disable DTL frequency loop */
> - MmioAnd32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
> -
> - /* Configure Generation 3 DFE */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_G3_SET4_REG,
> - ~HPIPE_GX_SET4_DFE_RES_MASK,
> - 0x3 << HPIPE_GX_SET4_DFE_RES_OFFSET
> - );
> -
> - /* Use TX/RX training result for DFE */
> - MmioAnd32 (HpipeAddr + HPIPE_DFE_REG0, ~HPIPE_DFE_RES_FORCE_MASK);
> -
> - /* Configure initial and final coefficient value for receiver */
> - MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data);
> - Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |
> - HPIPE_GX_SET1_RX_SELMUPP_MASK |
> - HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_MASK;
> - Data = 0x1 | (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data);
> -
> - /* Trigger sampler 5us enable pulse */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
> - ~HPIPE_SAMPLER_MASK,
> - 0x1 << HPIPE_SAMPLER_OFFSET
> - );
> - MicroSecondDelay (5);
> - MmioAnd32 (
> - HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
> - ~HPIPE_SAMPLER_MASK
> - );
> -
> - /* FFE resistor tuning for different bandwidth */
> - Mask = HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK |
> - HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK;
> - Data = (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) |
> - (0x3 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET3_REG, ~Mask, Data);
> -
> - /* Pattern lock lost timeout disable */
> - MmioAnd32 (HpipeAddr + HPIPE_FRAME_DETECT_CTRL_3_REG, ~HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK);
> -
> - /* Configure DFE adaptations */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_CDR_CONTROL_REG,
> - ~(HPIPE_CDR_MAX_DFE_ADAPT_1_MASK | HPIPE_CDR_MAX_DFE_ADAPT_0_MASK | HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK),
> - 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET
> - );
> - MmioAnd32 (HpipeAddr + HPIPE_DFE_CONTROL_REG, ~HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK);
> -
> - /* Hpipe Generation 2 setting 1*/
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_G2_SET1_REG,
> - ~(HPIPE_GX_SET1_RX_SELMUPI_MASK | HPIPE_GX_SET1_RX_SELMUPP_MASK | HPIPE_GX_SET1_RX_SELMUFI_MASK),
> - 0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET
> - );
> -
> - /* DFE enable */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_G2_SET4_REG,
> - ~HPIPE_GX_SET4_DFE_RES_MASK,
> - 0x3 << HPIPE_GX_SET4_DFE_RES_OFFSET
> - );
> -
> - /* Configure DFE Resolution */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_LANE_CFG4_REG,
> - ~HPIPE_LANE_CFG4_DFE_EN_SEL_MASK,
> - 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET
> - );
> -
> - /* VDD calibration control */
> - MmioAndThenOr32 (
> - HpipeAddr + HPIPE_VDD_CAL_CTRL_REG,
> - ~HPIPE_EXT_SELLV_RXSAMPL_MASK,
> - 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET
> - );
> -
> - /* Set PLL Charge-pump Current Control */
> - MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET5_REG, ~HPIPE_GX_SET5_ICP_MASK, 0x4);
> -
> - /* Set lane rqualization remote setting */
> - Mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK |
> - HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK |
> - HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
> - Data = (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) |
> - (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) |
> - (HPIPE_LANE_CFG_FOM_PRESET_VECTOR_DEFAULT);
> - MmioAndThenOr32 (HpipeAddr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, ~Mask, Data);
> -
> - /* Set phy in root complex mode */
> - MmioOr32 (HpipeAddr + HPIPE_LANE_EQU_CONFIG_0_REG, HPIPE_CFG_PHY_RC_EP_MASK);
> -}
> -
> -STATIC
> -EFI_STATUS
> -ComPhyPciePhyPowerUp (
> - IN UINT32 Lane,
> - IN UINT32 PcieWidth,
> - IN EFI_PHYSICAL_ADDRESS ComPhyBase,
> - IN EFI_PHYSICAL_ADDRESS HpipeBase
> -)
> -{
> - EFI_STATUS Status = EFI_SUCCESS;
> - UINT8 StartLane, EndLane, Loop;
> - UINT32 Data;
> -
> - /*
> - * For PCIe by4 or by2 - release from reset only after finish to
> - * configure all lanes
> - */
> - if ((PcieWidth == 1) || (Lane == (PcieWidth - 1))) {
> - if (PcieWidth != 1) {
> - /* Allows writing to all lanes in one write */
> - RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
> - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_ENABLE,
> - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
> - StartLane = 0;
> - EndLane = PcieWidth;
> -
> - /*
> - * Release from PIPE soft reset
> - * for PCIe by4 or by2 - release from soft reset
> - * all lanes - can't use read modify write
> - */
> - RegSet (HPIPE_ADDR (HpipeBase, 0) + HPIPE_RST_CLK_CTRL_REG,
> - HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 | HPIPE_RST_CLK_CTRL_MODE_REFDIV_4,
> - HPIPE_RST_CLK_CTRL_CLR_ALL_MASK);
> - } else {
> - StartLane = Lane;
> - EndLane = Lane + 1;
> -
> - /*
> - * Release from PIPE soft reset
> - * for PCIe by4 or by2 - release from soft reset
> - * all lanes
> - */
> - RegSet (HPIPE_ADDR (HpipeBase, Lane) + HPIPE_RST_CLK_CTRL_REG,
> - HPIPE_RST_CLK_CTRL_PIPE_RST_DISABLE,
> - HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
> - }
> -
> - if (PcieWidth != 1) {
> - /* Disable writing to all lanes with one write */
> - RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
> - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_DISABLE,
> - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
> - }
> - MemoryFence ();
> -
> - /* Wait 20ms until status of all lanes stabilize */
> - MicroSecondDelay (20000);
> -
> - /* Make sure all lanes are UP */
> - for (Loop = StartLane; Loop < EndLane; Loop++) {
> - Data = MmioRead32 (HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG);
> -
> - if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) {
> - DEBUG ((DEBUG_ERROR,
> - "%a: Read from lane%d, reg = %p - value = 0x%x\n",
> - __FUNCTION__,
> - Loop,
> - HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG,
> - Data));
> - DEBUG ((DEBUG_ERROR,
> - "%a: HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n",
> - __FUNCTION__));
> - Status = EFI_D_ERROR;
> - break;
> - }
> - }
> - }
> -
> - return Status;
> -}
> -
> -STATIC
> -EFI_STATUS
> -ComPhyPciePowerUp (
> - IN UINT8 ChipId,
> - IN UINT32 Lane,
> - IN UINT32 PcieWidth,
> - IN EFI_PHYSICAL_ADDRESS HpipeBase,
> - IN EFI_PHYSICAL_ADDRESS ComPhyBase
> - )
> -{
> - EFI_STATUS Status = EFI_SUCCESS;
> - EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
> - EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
> - UINT32 PcieClk;
> -
> - /*
> - * Obtain clock direction from sample-at-reset configuration.
> - * 4th and 5th SerDes lanes can belong only to PCIE Port1 and
> - * Port2, which use different clock type specifier than Port0.
> - */
> - if (Lane == 4 || Lane == 5) {
> - PcieClk = SampleAtResetGetPcieClockDirection (ChipId, CP110_PCIE_REF_CLK_TYPE12);
> - } else {
> - PcieClk = SampleAtResetGetPcieClockDirection (ChipId, CP110_PCIE_REF_CLK_TYPE0);
> - }
> -
> - DEBUG ((DEBUG_INFO, "%a: ChipId: %d PcieClk:%d\n", __FUNCTION__, ChipId, PcieClk));
> -
> - DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
> -
> - ComPhyPcieRFUConfiguration (Lane, PcieWidth, ComPhyAddr);
> -
> - DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
> -
> - ComPhyPciePhyConfiguration (Lane, PcieWidth, PcieClk, ComPhyAddr, HpipeAddr);
> -
> - DEBUG((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n"));
> -
> - ComPhyPcieSetAnalogParameters (HpipeAddr);
> -
> - DEBUG ((DEBUG_INFO, "%a: stage: ComPhy power up and check PLL\n", __FUNCTION__));
> -
> - Status = ComPhyPciePhyPowerUp (Lane, PcieWidth, ComPhyBase, HpipeBase);
> -
> - return Status;
> -}
> -
> -STATIC
> -VOID
> ComPhyUsb3RFUConfiguration (
> IN EFI_PHYSICAL_ADDRESS ComPhyAddr
> )
> @@ -1229,7 +745,12 @@ ComPhyCp110Init (
> case COMPHY_TYPE_PCIE1:
> case COMPHY_TYPE_PCIE2:
> case COMPHY_TYPE_PCIE3:
> - Status = ComPhyPciePowerUp (ChipId, Lane, PcieWidth, HpipeBaseAddr, ComPhyBaseAddr);
> + Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
> + PtrChipCfg->ComPhyBaseAddr,
> + Lane,
> + COMPHY_FW_PCIE_FORMAT (PcieWidth,
> + COMPHY_PCIE_MODE,
> + PtrComPhyMap->Speed));
> break;
> case COMPHY_TYPE_SATA0:
> case COMPHY_TYPE_SATA1:
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [platforms: PATCH 2/6] Marvell/Library: ComPhyLib: Configure PCIE in ARM-TF
2018-07-25 10:01 ` Ard Biesheuvel
@ 2018-07-25 10:32 ` Marcin Wojtas
0 siblings, 0 replies; 11+ messages in thread
From: Marcin Wojtas @ 2018-07-25 10:32 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel@lists.01.org, Leif Lindholm, Nadav Haklai,
Jan Dąbroś, Grzegorz Jaszczyk
2018-07-25 12:01 GMT+02:00 Ard Biesheuvel <ard.biesheuvel@linaro.org>:
> On 13 July 2018 at 16:09, Marcin Wojtas <mw@semihalf.com> wrote:
>> From: Grzegorz Jaszczyk <jaz@semihalf.com>
>>
>> Replace the ComPhy initialization for PCIE with appropriate SMC call,
>> so the firmware will execute required serdes configuration.
>>
>
> 'the firmware' ?
Will change to 'ARMT-TF' then.
Best regards,
Marcin
>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> ---
>> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h | 22 -
>> Silicon/Marvell/Include/Library/SampleAtResetLib.h | 7 -
>> Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 3 +-
>> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c | 19 -
>> Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 491 +-------------------
>> 5 files changed, 8 insertions(+), 534 deletions(-)
>>
>> diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h
>> index 323399f..e47396d 100644
>> --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h
>> +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h
>> @@ -44,18 +44,6 @@ SAR - Sample At Reset
>>
>> #define CP110_SAR_BASE(_CpIndex) (0xf2000000 + (0x2000000 * (_CpIndex)) + 0x400200)
>>
>> -#define MAX_CP_COUNT 2
>> -#define MAX_PCIE_CLK_TYPE_COUNT 2
>> -
>> -#define CP0_PCIE0_CLK_OFFSET 2
>> -#define CP0_PCIE1_CLK_OFFSET 3
>> -#define CP1_PCIE0_CLK_OFFSET 0
>> -#define CP1_PCIE1_CLK_OFFSET 1
>> -#define CP0_PCIE0_CLK_MASK (1 << CP0_PCIE0_CLK_OFFSET)
>> -#define CP0_PCIE1_CLK_MASK (1 << CP0_PCIE1_CLK_OFFSET)
>> -#define CP1_PCIE0_CLK_MASK (1 << CP1_PCIE0_CLK_OFFSET)
>> -#define CP1_PCIE1_CLK_MASK (1 << CP1_PCIE1_CLK_OFFSET)
>> -
>> typedef enum {
>> CPU_2000_DDR_1200_RCLK_1200 = 0x0,
>> CPU_2000_DDR_1050_RCLK_1050 = 0x1,
>> @@ -97,13 +85,3 @@ STATIC CONST PLL_FREQUENCY_DESCRIPTION PllFrequencyTable[SAR_MAX_OPTIONS] = {
>> {800 , 800 , 800 , CPU_800_DDR_800_RCLK_800},
>> {1000, 800 , 800 , CPU_1000_DDR_800_RCLK_800}
>> };
>> -
>> -STATIC CONST UINT32 PcieClockMask[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT] = {
>> - {CP0_PCIE0_CLK_MASK, CP0_PCIE1_CLK_MASK},
>> - {CP1_PCIE0_CLK_MASK, CP1_PCIE1_CLK_MASK}
>> -};
>> -
>> -STATIC CONST UINT32 PcieClockOffset[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT] = {
>> - {CP0_PCIE0_CLK_OFFSET, CP0_PCIE1_CLK_OFFSET},
>> - {CP1_PCIE0_CLK_OFFSET, CP1_PCIE1_CLK_OFFSET}
>> -};
>> diff --git a/Silicon/Marvell/Include/Library/SampleAtResetLib.h b/Silicon/Marvell/Include/Library/SampleAtResetLib.h
>> index 1be3a6a..1e7b27c 100644
>> --- a/Silicon/Marvell/Include/Library/SampleAtResetLib.h
>> +++ b/Silicon/Marvell/Include/Library/SampleAtResetLib.h
>> @@ -47,11 +47,4 @@ SampleAtResetGetDramFrequency (
>> VOID
>> );
>>
>> -UINT32
>> -EFIAPI
>> -SampleAtResetGetPcieClockDirection (
>> - IN UINT32 CpIndex,
>> - IN UINT32 PcieIndex
>> - );
>> -
>> #endif /* __SAMPLE_AT_RESET_LIB_H__ */
>> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
>> index 34c1e9b..20a9767 100644
>> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
>> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
>> @@ -125,7 +125,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>>
>> #define COMPHY_FW_FORMAT(mode, idx, speeds) \
>> ((mode << 12) | (idx << 8) | (speeds << 2))
>> -
>> +#define COMPHY_FW_PCIE_FORMAT(pcie_width, mode, speeds) \
>> + ((pcie_width << 18) | COMPHY_FW_FORMAT (mode, 0, speeds))
>>
>> #define COMPHY_POLARITY_NO_INVERT 0
>> #define COMPHY_POLARITY_TXD_INVERT 1
>> diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c
>> index 3ebff56..5a9a5f9 100644
>> --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c
>> +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c
>> @@ -90,22 +90,3 @@ SampleAtResetGetDramFrequency (
>>
>> return PllFrequencies->DdrFrequency;
>> }
>> -
>> -UINT32
>> -EFIAPI
>> -SampleAtResetGetPcieClockDirection (
>> - IN UINT32 CpIndex,
>> - IN UINT32 PcieIndex
>> - )
>> -{
>> - UINT32 ClockDirection;
>> -
>> - ASSERT (CpIndex < MAX_CP_COUNT);
>> - ASSERT (PcieIndex < MAX_PCIE_CLK_TYPE_COUNT);
>> -
>> - ClockDirection = MmioAnd32 (CP110_SAR_BASE (CpIndex),
>> - PcieClockMask[CpIndex][PcieIndex] >>
>> - PcieClockOffset[CpIndex][PcieIndex]);
>> -
>> - return ClockDirection;
>> -}
>> diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
>> index 4b8b27a..6cefee9 100755
>> --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
>> +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
>> @@ -46,9 +46,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>> #define HPIPE_ADDR(base, Lane) (SD_ADDR(base, Lane) + HPIPE_ADDR_OFFSET)
>> #define COMPHY_ADDR(base, Lane) (base + COMPHY_ADDR_LANE_WIDTH * Lane)
>>
>> -#define CP110_PCIE_REF_CLK_TYPE0 0
>> -#define CP110_PCIE_REF_CLK_TYPE12 1
>> -
>> /*
>> * For CP-110 we have 2 Selector registers "PHY Selectors"
>> * and " PIPE Selectors".
>> @@ -103,487 +100,6 @@ COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {
>>
>> STATIC
>> VOID
>> -ComPhyPcieRFUConfiguration (
>> - IN UINT32 Lane,
>> - IN UINT32 PcieWidth,
>> - IN EFI_PHYSICAL_ADDRESS ComPhyAddr
>> -)
>> -{
>> - UINT32 Mask, Data;
>> -
>> - /* Enable PCIe by4 and by2 */
>> - if (Lane == 0) {
>> - if (PcieWidth == 4) {
>> - RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
>> - COMMON_PHY_SD_CTRL1_PCIE_X4_EN,
>> - COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK);
>> - } else if (PcieWidth == 2) {
>> - RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1,
>> - COMMON_PHY_SD_CTRL1_PCIE_X2_EN,
>> - COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK);
>> - }
>> - }
>> -
>> - /* RFU configurations - hard reset ComPhy */
>> - Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
>> - Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
>> - Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
>> - Data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
>> - Mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
>> - Data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
>> - Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
>> - Data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
>> - Mask |= COMMON_PHY_PHY_MODE_MASK;
>> - Data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET;
>> - RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
>> -
>> - /* Release from hard reset */
>> - Mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
>> - Data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
>> - Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
>> - Data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
>> - RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
>> -
>> - /* Wait 1ms - until band gap and ref clock ready */
>> - MicroSecondDelay (1000);
>> - MemoryFence ();
>> -}
>> -
>> -STATIC
>> -VOID
>> -ComPhyPciePhyConfiguration (
>> - IN UINT32 Lane,
>> - IN UINT32 PcieWidth,
>> - IN UINT32 PcieClk,
>> - IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
>> - IN EFI_PHYSICAL_ADDRESS HpipeAddr
>> -)
>> -{
>> - UINT32 Mask, Data;
>> -
>> - /* Set PIPE soft reset */
>> - Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
>> - Data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
>> -
>> - /* Set PHY Datapath width mode for V0 */
>> - Mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
>> - Data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
>> -
>> - /* Set Data bus width USB mode for V0 */
>> - Mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
>> - Data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
>> -
>> - /* Set CORE_CLK output frequency for 250Mhz */
>> - Mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
>> - Data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
>> - RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask);
>> -
>> - /* Set PLL ready delay for 0x2 */
>> - Data = HPIPE_CLK_SRC_LO_PLL_RDY_DL_DEFAULT;
>> - Mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
>> - if (PcieWidth != 1) {
>> - Data |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_DEFAULT |
>> - HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_DEFAULT;
>> - Mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK |
>> - HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
>> - }
>> - RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, Data, Mask);
>> -
>> - /* Set PIPE mode interface to PCIe3 - 0x1 */
>> - Data = HPIPE_CLK_SRC_HI_MODE_PIPE_EN;
>> - Mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
>> - if (PcieWidth != 1) {
>> - Mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK |
>> - HPIPE_CLK_SRC_HI_LANE_MASTER_MASK |
>> - HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
>> - if (Lane == 0) {
>> - Data |= HPIPE_CLK_SRC_HI_LANE_STRT_EN |
>> - HPIPE_CLK_SRC_HI_LANE_MASTER_EN;
>> - } else if (Lane == (PcieWidth - 1)) {
>> - Data |= HPIPE_CLK_SRC_HI_LANE_BREAK_EN;
>> - }
>> - }
>> - RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, Data, Mask);
>> -
>> - /* Config update polarity equalization */
>> - RegSet (HpipeAddr + HPIPE_LANE_EQ_CFG1_REG,
>> - 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET, HPIPE_CFG_UPDATE_POLARITY_MASK);
>> -
>> - /* Set PIPE version 4 to mode enable */
>> - RegSet (HpipeAddr + HPIPE_DFE_CTRL_28_REG,
>> - 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, HPIPE_DFE_CTRL_28_PIPE4_MASK);
>> -
>> - /* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz clock */
>> - Mask = HPIPE_MISC_TXDCLK_2X_MASK;
>> - Data = HPIPE_MISC_TXDCLK_2X_500MHZ;
>> -
>> - /* Enable 500MHz Clock */
>> - Mask |= HPIPE_MISC_CLK500_EN_MASK;
>> - Data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
>> -
>> - if (PcieClk) {
>> - /*
>> - * Enable PIN clock 100M_125M
>> - * Only if clock is output, configure the clock-source mux
>> - */
>> - Mask |= HPIPE_MISC_CLK100M_125M_MASK;
>> - Data |= HPIPE_MISC_CLK100M_125M_EN;
>> - /* Set reference clock comes from group 1 */
>> - Mask |= HPIPE_MISC_REFCLK_SEL_MASK;
>> - Data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
>> - } else {
>> - /* Set reference clock comes from group 2 */
>> - Mask |= HPIPE_MISC_REFCLK_SEL_MASK;
>> - Data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
>> - }
>> -
>> - /* Force ICP */
>> - Mask |= HPIPE_MISC_ICP_FORCE_MASK;
>> - Data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
>> - RegSet (HpipeAddr + HPIPE_MISC_REG, Data, Mask);
>> -
>> - if (PcieClk) {
>> - /* Set reference frequcency select - 0x2 for 25MHz*/
>> - Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
>> - Data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
>> - } else {
>> - /* Set reference frequcency select - 0x0 for 100MHz*/
>> - Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
>> - Data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
>> - }
>> -
>> - /* Set PHY mode to PCIe */
>> - Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
>> - Data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
>> - RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
>> -
>> - /* Ref clock alignment */
>> - if (PcieWidth != 1) {
>> - RegSet (HpipeAddr + HPIPE_LANE_ALIGN_REG,
>> - HPIPE_LANE_ALIGN_OFF,
>> - HPIPE_LANE_ALIGN_OFF_MASK);
>> - }
>> -
>> - /*
>> - * Set the amount of time spent in the LoZ state - set
>> - * for 0x7 only if the PCIe clock is output
>> - */
>> - if (PcieClk)
>> - RegSet (HpipeAddr + HPIPE_GLOBAL_PM_CTRL,
>> - 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
>> - HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
>> -
>> - /* Set Maximal PHY Generation Setting (8Gbps) */
>> - Mask = HPIPE_INTERFACE_GEN_MAX_MASK;
>> - Data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
>> - /* Bypass frame detection and sync detection for RX DATA */
>> - Mask |= HPIPE_INTERFACE_DET_BYPASS_MASK;
>> - Data |= 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET;
>> - /* Set Link Train Mode (Tx training control pins are used) */
>> - Mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
>> - Data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
>> - RegSet (HpipeAddr + HPIPE_INTERFACE_REG, Data, Mask);
>> -
>> - /* Set Idle_sync enable */
>> - Mask = HPIPE_PCIE_IDLE_SYNC_MASK;
>> - Data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET;
>> -
>> - /* Select bits for PCIE Gen3(32bit) */
>> - Mask |= HPIPE_PCIE_SEL_BITS_MASK;
>> - Data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET;
>> - RegSet (HpipeAddr + HPIPE_PCIE_REG0, Data, Mask);
>> -
>> - /* Enable Tx_adapt_g1 */
>> - Mask = HPIPE_TX_TRAIN_CTRL_G1_MASK;
>> - Data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET;
>> -
>> - /* Enable Tx_adapt_gn1 */
>> - Mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK;
>> - Data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET;
>> -
>> - /* Disable Tx_adapt_g0 */
>> - Mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK;
>> - Data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
>> - RegSet (HpipeAddr + HPIPE_TX_TRAIN_CTRL_REG, Data, Mask);
>> -
>> - /* Set reg_tx_train_chk_init */
>> - Mask = HPIPE_TX_TRAIN_CHK_INIT_MASK;
>> - Data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET;
>> -
>> - /* Enable TX_COE_FM_PIN_PCIE3_EN */
>> - Mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK;
>> - Data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET;
>> - RegSet (HpipeAddr + HPIPE_TX_TRAIN_REG, Data, Mask);
>> -}
>> -
>> -STATIC
>> -VOID
>> -ComPhyPcieSetAnalogParameters (
>> - IN EFI_PHYSICAL_ADDRESS HpipeAddr
>> -)
>> -{
>> - UINT32 Data, Mask;
>> -
>> - /* Set preset sweep configurations */
>> - Mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK |
>> - HPIPE_TX_NUM_OF_PRESET_MASK |
>> - HPIPE_TX_SWEEP_PRESET_EN_MASK;
>> - Data = (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) |
>> - (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) |
>> - (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET);
>> - MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_11_REG, ~Mask, Data);
>> -
>> - /* Tx train start configuration */
>> - Mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK |
>> - HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK |
>> - HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK |
>> - HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK;
>> - Data = (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) |
>> - (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET);
>> - MmioAndThenOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_5_REG, ~Mask, Data);
>> -
>> - /* Enable Tx train P2P */
>> - MmioOr32 (HpipeAddr + HPIPE_TX_TRAIN_CTRL_0_REG, HPIPE_TX_TRAIN_P2P_HOLD_MASK);
>> -
>> - /* Configure Tx train timeout */
>> - MmioAndThenOr32 (
>> - HpipeAddr + HPIPE_TX_TRAIN_CTRL_4_REG,
>> - ~HPIPE_TRX_TRAIN_TIMER_MASK,
>> - 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET
>> - );
>> -
>> - /* Disable G0/G1/GN1 adaptation */
>> - MmioAnd32 (
>> - HpipeAddr + HPIPE_TX_TRAIN_CTRL_REG,
>> - ~(HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK | HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
>> - );
>> -
>> - /* Disable DTL frequency loop */
>> - MmioAnd32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
>> -
>> - /* Configure Generation 3 DFE */
>> - MmioAndThenOr32 (
>> - HpipeAddr + HPIPE_G3_SET4_REG,
>> - ~HPIPE_GX_SET4_DFE_RES_MASK,
>> - 0x3 << HPIPE_GX_SET4_DFE_RES_OFFSET
>> - );
>> -
>> - /* Use TX/RX training result for DFE */
>> - MmioAnd32 (HpipeAddr + HPIPE_DFE_REG0, ~HPIPE_DFE_RES_FORCE_MASK);
>> -
>> - /* Configure initial and final coefficient value for receiver */
>> - MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data);
>> - Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |
>> - HPIPE_GX_SET1_RX_SELMUPP_MASK |
>> - HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_MASK;
>> - Data = 0x1 | (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET);
>> - MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data);
>> -
>> - /* Trigger sampler 5us enable pulse */
>> - MmioAndThenOr32 (
>> - HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
>> - ~HPIPE_SAMPLER_MASK,
>> - 0x1 << HPIPE_SAMPLER_OFFSET
>> - );
>> - MicroSecondDelay (5);
>> - MmioAnd32 (
>> - HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG,
>> - ~HPIPE_SAMPLER_MASK
>> - );
>> -
>> - /* FFE resistor tuning for different bandwidth */
>> - Mask = HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK |
>> - HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK;
>> - Data = (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) |
>> - (0x3 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET);
>> - MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET3_REG, ~Mask, Data);
>> -
>> - /* Pattern lock lost timeout disable */
>> - MmioAnd32 (HpipeAddr + HPIPE_FRAME_DETECT_CTRL_3_REG, ~HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK);
>> -
>> - /* Configure DFE adaptations */
>> - MmioAndThenOr32 (
>> - HpipeAddr + HPIPE_CDR_CONTROL_REG,
>> - ~(HPIPE_CDR_MAX_DFE_ADAPT_1_MASK | HPIPE_CDR_MAX_DFE_ADAPT_0_MASK | HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK),
>> - 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET
>> - );
>> - MmioAnd32 (HpipeAddr + HPIPE_DFE_CONTROL_REG, ~HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK);
>> -
>> - /* Hpipe Generation 2 setting 1*/
>> - MmioAndThenOr32 (
>> - HpipeAddr + HPIPE_G2_SET1_REG,
>> - ~(HPIPE_GX_SET1_RX_SELMUPI_MASK | HPIPE_GX_SET1_RX_SELMUPP_MASK | HPIPE_GX_SET1_RX_SELMUFI_MASK),
>> - 0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET
>> - );
>> -
>> - /* DFE enable */
>> - MmioAndThenOr32 (
>> - HpipeAddr + HPIPE_G2_SET4_REG,
>> - ~HPIPE_GX_SET4_DFE_RES_MASK,
>> - 0x3 << HPIPE_GX_SET4_DFE_RES_OFFSET
>> - );
>> -
>> - /* Configure DFE Resolution */
>> - MmioAndThenOr32 (
>> - HpipeAddr + HPIPE_LANE_CFG4_REG,
>> - ~HPIPE_LANE_CFG4_DFE_EN_SEL_MASK,
>> - 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET
>> - );
>> -
>> - /* VDD calibration control */
>> - MmioAndThenOr32 (
>> - HpipeAddr + HPIPE_VDD_CAL_CTRL_REG,
>> - ~HPIPE_EXT_SELLV_RXSAMPL_MASK,
>> - 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET
>> - );
>> -
>> - /* Set PLL Charge-pump Current Control */
>> - MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET5_REG, ~HPIPE_GX_SET5_ICP_MASK, 0x4);
>> -
>> - /* Set lane rqualization remote setting */
>> - Mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK |
>> - HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK |
>> - HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
>> - Data = (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) |
>> - (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) |
>> - (HPIPE_LANE_CFG_FOM_PRESET_VECTOR_DEFAULT);
>> - MmioAndThenOr32 (HpipeAddr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, ~Mask, Data);
>> -
>> - /* Set phy in root complex mode */
>> - MmioOr32 (HpipeAddr + HPIPE_LANE_EQU_CONFIG_0_REG, HPIPE_CFG_PHY_RC_EP_MASK);
>> -}
>> -
>> -STATIC
>> -EFI_STATUS
>> -ComPhyPciePhyPowerUp (
>> - IN UINT32 Lane,
>> - IN UINT32 PcieWidth,
>> - IN EFI_PHYSICAL_ADDRESS ComPhyBase,
>> - IN EFI_PHYSICAL_ADDRESS HpipeBase
>> -)
>> -{
>> - EFI_STATUS Status = EFI_SUCCESS;
>> - UINT8 StartLane, EndLane, Loop;
>> - UINT32 Data;
>> -
>> - /*
>> - * For PCIe by4 or by2 - release from reset only after finish to
>> - * configure all lanes
>> - */
>> - if ((PcieWidth == 1) || (Lane == (PcieWidth - 1))) {
>> - if (PcieWidth != 1) {
>> - /* Allows writing to all lanes in one write */
>> - RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
>> - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_ENABLE,
>> - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
>> - StartLane = 0;
>> - EndLane = PcieWidth;
>> -
>> - /*
>> - * Release from PIPE soft reset
>> - * for PCIe by4 or by2 - release from soft reset
>> - * all lanes - can't use read modify write
>> - */
>> - RegSet (HPIPE_ADDR (HpipeBase, 0) + HPIPE_RST_CLK_CTRL_REG,
>> - HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 | HPIPE_RST_CLK_CTRL_MODE_REFDIV_4,
>> - HPIPE_RST_CLK_CTRL_CLR_ALL_MASK);
>> - } else {
>> - StartLane = Lane;
>> - EndLane = Lane + 1;
>> -
>> - /*
>> - * Release from PIPE soft reset
>> - * for PCIe by4 or by2 - release from soft reset
>> - * all lanes
>> - */
>> - RegSet (HPIPE_ADDR (HpipeBase, Lane) + HPIPE_RST_CLK_CTRL_REG,
>> - HPIPE_RST_CLK_CTRL_PIPE_RST_DISABLE,
>> - HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
>> - }
>> -
>> - if (PcieWidth != 1) {
>> - /* Disable writing to all lanes with one write */
>> - RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1,
>> - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_DISABLE,
>> - COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
>> - }
>> - MemoryFence ();
>> -
>> - /* Wait 20ms until status of all lanes stabilize */
>> - MicroSecondDelay (20000);
>> -
>> - /* Make sure all lanes are UP */
>> - for (Loop = StartLane; Loop < EndLane; Loop++) {
>> - Data = MmioRead32 (HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG);
>> -
>> - if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) {
>> - DEBUG ((DEBUG_ERROR,
>> - "%a: Read from lane%d, reg = %p - value = 0x%x\n",
>> - __FUNCTION__,
>> - Loop,
>> - HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG,
>> - Data));
>> - DEBUG ((DEBUG_ERROR,
>> - "%a: HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n",
>> - __FUNCTION__));
>> - Status = EFI_D_ERROR;
>> - break;
>> - }
>> - }
>> - }
>> -
>> - return Status;
>> -}
>> -
>> -STATIC
>> -EFI_STATUS
>> -ComPhyPciePowerUp (
>> - IN UINT8 ChipId,
>> - IN UINT32 Lane,
>> - IN UINT32 PcieWidth,
>> - IN EFI_PHYSICAL_ADDRESS HpipeBase,
>> - IN EFI_PHYSICAL_ADDRESS ComPhyBase
>> - )
>> -{
>> - EFI_STATUS Status = EFI_SUCCESS;
>> - EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
>> - EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
>> - UINT32 PcieClk;
>> -
>> - /*
>> - * Obtain clock direction from sample-at-reset configuration.
>> - * 4th and 5th SerDes lanes can belong only to PCIE Port1 and
>> - * Port2, which use different clock type specifier than Port0.
>> - */
>> - if (Lane == 4 || Lane == 5) {
>> - PcieClk = SampleAtResetGetPcieClockDirection (ChipId, CP110_PCIE_REF_CLK_TYPE12);
>> - } else {
>> - PcieClk = SampleAtResetGetPcieClockDirection (ChipId, CP110_PCIE_REF_CLK_TYPE0);
>> - }
>> -
>> - DEBUG ((DEBUG_INFO, "%a: ChipId: %d PcieClk:%d\n", __FUNCTION__, ChipId, PcieClk));
>> -
>> - DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
>> -
>> - ComPhyPcieRFUConfiguration (Lane, PcieWidth, ComPhyAddr);
>> -
>> - DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
>> -
>> - ComPhyPciePhyConfiguration (Lane, PcieWidth, PcieClk, ComPhyAddr, HpipeAddr);
>> -
>> - DEBUG((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n"));
>> -
>> - ComPhyPcieSetAnalogParameters (HpipeAddr);
>> -
>> - DEBUG ((DEBUG_INFO, "%a: stage: ComPhy power up and check PLL\n", __FUNCTION__));
>> -
>> - Status = ComPhyPciePhyPowerUp (Lane, PcieWidth, ComPhyBase, HpipeBase);
>> -
>> - return Status;
>> -}
>> -
>> -STATIC
>> -VOID
>> ComPhyUsb3RFUConfiguration (
>> IN EFI_PHYSICAL_ADDRESS ComPhyAddr
>> )
>> @@ -1229,7 +745,12 @@ ComPhyCp110Init (
>> case COMPHY_TYPE_PCIE1:
>> case COMPHY_TYPE_PCIE2:
>> case COMPHY_TYPE_PCIE3:
>> - Status = ComPhyPciePowerUp (ChipId, Lane, PcieWidth, HpipeBaseAddr, ComPhyBaseAddr);
>> + Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
>> + PtrChipCfg->ComPhyBaseAddr,
>> + Lane,
>> + COMPHY_FW_PCIE_FORMAT (PcieWidth,
>> + COMPHY_PCIE_MODE,
>> + PtrComPhyMap->Speed));
>> break;
>> case COMPHY_TYPE_SATA0:
>> case COMPHY_TYPE_SATA1:
>> --
>> 2.7.4
>>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [platforms: PATCH 3/6] Marvell/Library: ComPhyLib: Configure RXAUI in ARM-TF
2018-07-13 14:09 [platforms: PATCH 0/6] Armada7k8k ComPhy rework Marcin Wojtas
2018-07-13 14:09 ` [platforms: PATCH 1/6] Marvell/Library: ComPhyLib: Configure SATA, SGMII and SFI in ARM-TF Marcin Wojtas
2018-07-13 14:09 ` [platforms: PATCH 2/6] Marvell/Library: ComPhyLib: Configure PCIE " Marcin Wojtas
@ 2018-07-13 14:09 ` Marcin Wojtas
2018-07-13 14:09 ` [platforms: PATCH 4/6] Marvell/Library: ComPhyLib: Configure USB " Marcin Wojtas
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Marcin Wojtas @ 2018-07-13 14:09 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Replace the comphy initialization for RXAUI with appropriate SMC call,
so the firmware will execute required serdes configuration.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 1 +
Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 257 +-------------------
2 files changed, 5 insertions(+), 253 deletions(-)
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
index 20a9767..972cbbb 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
@@ -123,6 +123,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define MV_SIP_COMPHY_POWER_OFF 0x82000002
#define MV_SIP_COMPHY_PLL_LOCK 0x82000003
+#define COMPHY_FW_MODE_FORMAT(mode) (mode << 12)
#define COMPHY_FW_FORMAT(mode, idx, speeds) \
((mode << 12) | (idx << 8) | (speeds << 2))
#define COMPHY_FW_PCIE_FORMAT(pcie_width, mode, speeds) \
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
index 6cefee9..c46cad1 100755
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
@@ -261,27 +261,6 @@ ComphyUsb3PowerUp (
}
STATIC
-UINT32
-PollingWithTimeout (
- IN EFI_PHYSICAL_ADDRESS Addr,
- IN UINT32 Val,
- IN UINT32 Mask,
- IN UINT64 Usec_timeout
- )
-{
- UINT32 Data;
-
- do {
- MicroSecondDelay(1);
- Data = MmioRead32(Addr) & Mask;
- } while (Data != Val && --Usec_timeout > 0);
-
- if (Usec_timeout == 0)
- return Data;
- return 0;
-}
-
-STATIC
VOID
ComPhySataMacPowerDown (
IN EFI_PHYSICAL_ADDRESS SataBase
@@ -424,237 +403,6 @@ ComPhySataPowerUp (
}
STATIC
-EFI_STATUS
-ComPhyEthCommonRFUPowerUp (
- IN EFI_PHYSICAL_ADDRESS SdIpAddr
-)
-{
- EFI_STATUS Status = EFI_SUCCESS;
- UINT32 Mask, Data;
- EFI_PHYSICAL_ADDRESS Addr;
-
- /* SerDes External Configuration */
- Mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
- Data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
- Mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
- Data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
- Mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
- Data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
- RegSet (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, Data, Mask);
-
- /* Check PLL rx & tx ready */
- Addr = SdIpAddr + SD_EXTERNAL_STATUS0_REG;
- Data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | SD_EXTERNAL_STATUS0_PLL_TX_MASK;
- Mask = Data;
- Data = PollingWithTimeout (Addr, Data, Mask, 15000);
- if (Data != 0) {
- DEBUG((DEBUG_ERROR, "ComPhy: Read from reg = %p - value = 0x%x\n",
- SdIpAddr + SD_EXTERNAL_STATUS0_REG, Data));
- DEBUG((DEBUG_ERROR, "ComPhy: SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
- (Data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
- (Data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)));
- Status = EFI_D_ERROR;
- }
-
- /* RX init */
- Mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
- Data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
- RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask);
-
- /* Check that RX init done */
- Addr = SdIpAddr + SD_EXTERNAL_STATUS0_REG;
- Data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
- Mask = Data;
- Data = PollingWithTimeout (Addr, Data, Mask, 100);
- if (Data != 0) {
- DEBUG((DEBUG_ERROR, "ComPhy: Read from reg = %p - value = 0x%x\n",
- SdIpAddr + SD_EXTERNAL_STATUS0_REG, Data));
- DEBUG((DEBUG_ERROR, "ComPhy: SD_EXTERNAL_STATUS0_RX_INIT is 0\n"));
- Status = EFI_D_ERROR;
- }
- Mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
- Data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
- Mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
- Data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
- RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask);
-
- return Status;
-}
-
-STATIC
-EFI_STATUS
-ComPhyRxauiRFUConfiguration (
- IN UINT32 Lane,
- IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
- IN EFI_PHYSICAL_ADDRESS SdIpAddr
-)
-{
- UINT32 Mask, Data;
-
- MmioAndThenOr32 (
- ComPhyAddr + COMMON_PHY_CFG1_REG,
- ~(COMMON_PHY_CFG1_PWR_UP_MASK | COMMON_PHY_CFG1_PIPE_SELECT_MASK),
- COMMON_PHY_CFG1_PWR_UP_MASK
- );
-
- switch (Lane) {
- case 2:
- case 4:
- MmioOr32 (ComPhyAddr + COMMON_PHY_SD_CTRL1, COMMON_PHY_SD_CTRL1_RXAUI0_MASK);
- case 3:
- case 5:
- MmioOr32 (ComPhyAddr + COMMON_PHY_SD_CTRL1, COMMON_PHY_SD_CTRL1_RXAUI1_MASK);
- break;
- default:
- DEBUG ((DEBUG_ERROR, "RXAUI used on invalid lane %d\n", Lane));
- return EFI_INVALID_PARAMETER;
- }
-
- /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
- Mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK |
- SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK |
- SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK |
- SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK |
- SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK |
- SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK |
- SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK;
- Data = (0xb << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) |
- (0xb << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) |
- (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET);
- MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, ~Mask, Data);
-
- /* Release from hard reset */
- Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK |
- SD_EXTERNAL_CONFIG1_RESET_CORE_MASK |
- SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
- Data = SD_EXTERNAL_CONFIG1_RESET_IN_MASK |
- SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- MmioAndThenOr32 (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, ~Mask, Data);
-
- /* Wait 1ms - until band gap and ref clock are ready */
- MicroSecondDelay (1000);
- MemoryFence ();
-
- return EFI_SUCCESS;
-}
-
-STATIC
-VOID
-ComPhyRxauiPhyConfiguration (
- IN EFI_PHYSICAL_ADDRESS HpipeAddr
-)
-{
- /* Set reference clock */
- MmioAnd32 (HpipeAddr + HPIPE_MISC_REG, ~HPIPE_MISC_REFCLK_SEL_MASK);
-
- /* Power and PLL Control */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_PWR_PLL_REG,
- ~(HPIPE_PWR_PLL_REF_FREQ_MASK | HPIPE_PWR_PLL_PHY_MODE_MASK),
- 0x1 | (0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
- );
-
- /* Loopback register */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_LOOPBACK_REG,
- ~HPIPE_LOOPBACK_SEL_MASK,
- 0x1 << HPIPE_LOOPBACK_SEL_OFFSET
- );
-
- /* Rx control 1 */
- MmioOr32 (
- HpipeAddr + HPIPE_RX_CONTROL_1_REG,
- HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK | HPIPE_RX_CONTROL_1_CLK8T_EN_MASK
- );
-
- /* DTL Control */
- MmioAnd32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
-}
-
-STATIC
-VOID
-ComPhyRxauiSetAnalogParameters (
- IN EFI_PHYSICAL_ADDRESS HpipeAddr,
- IN EFI_PHYSICAL_ADDRESS SdIpAddr
-)
-{
- UINT32 Mask, Data;
-
- /* SERDES External Configuration 2 */
- MmioOr32 (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
-
- /* DFE Resolution control */
- MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK);
-
- /* Generation 1 setting_0 */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_G1_SET0_REG,
- ~HPIPE_GX_SET0_TX_EMPH1_MASK,
- 0xe << HPIPE_GX_SET0_TX_EMPH1_OFFSET
- );
-
- /* Generation 1 setting 1 */
- Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK |
- HPIPE_GX_SET1_RX_SELMUPP_MASK |
- HPIPE_GX_SET1_RX_DFE_EN_MASK;
- Data = 0x1 |
- (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) |
- (0x1 << HPIPE_GX_SET1_RX_DFE_EN_OFFSET);
- MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET1_REG, ~Mask, Data);
-
- /* DFE F3-F5 Coefficient Control */
- MmioAnd32 (
- HpipeAddr + HPIPE_DFE_F3_F5_REG,
- ~(HPIPE_DFE_F3_F5_DFE_EN_MASK | HPIPE_DFE_F3_F5_DFE_CTRL_MASK)
- );
-
- /* Configure Generation 1 setting 4 (DFE) */
- MmioAndThenOr32 (
- HpipeAddr + HPIPE_G1_SET4_REG,
- ~HPIPE_GX_SET4_DFE_RES_MASK,
- 0x1 << HPIPE_GX_SET4_DFE_RES_OFFSET
- );
-
- /* Generation 1 setting 3 */
- MmioOr32 (HpipeAddr + HPIPE_G1_SET3_REG, HPIPE_GX_SET3_FBCK_SEL_MASK);
-}
-
-STATIC
-EFI_STATUS
-ComPhyRxauiPowerUp (
- IN UINT32 Lane,
- IN EFI_PHYSICAL_ADDRESS HpipeBase,
- IN EFI_PHYSICAL_ADDRESS ComPhyBase
- )
-{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
- EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane);
- EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
-
- DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
-
- Status = ComPhyRxauiRFUConfiguration (Lane, ComPhyAddr, SdIpAddr);
- if (EFI_ERROR(Status)) {
- return Status;
- }
-
- DEBUG ((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
-
- ComPhyRxauiPhyConfiguration (HpipeAddr);
-
- DEBUG ((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n"));
-
- ComPhyRxauiSetAnalogParameters (HpipeAddr, SdIpAddr);
-
- DEBUG ((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx,Rx\n"));
-
- Status = ComPhyEthCommonRFUPowerUp (SdIpAddr);
-
- return Status;
-}
-
-STATIC
VOID
ComPhyMuxCp110 (
IN CHIP_COMPHY_CONFIG *PtrChipCfg,
@@ -803,7 +551,10 @@ ComPhyCp110Init (
break;
case COMPHY_TYPE_RXAUI0:
case COMPHY_TYPE_RXAUI1:
- Status = ComPhyRxauiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr);
+ Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
+ PtrChipCfg->ComPhyBaseAddr,
+ Lane,
+ COMPHY_FW_MODE_FORMAT (COMPHY_RXAUI_MODE));
break;
default:
DEBUG((DEBUG_ERROR, "Unknown SerDes Type, skip initialize SerDes %d\n",
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [platforms: PATCH 4/6] Marvell/Library: ComPhyLib: Configure USB in ARM-TF
2018-07-13 14:09 [platforms: PATCH 0/6] Armada7k8k ComPhy rework Marcin Wojtas
` (2 preceding siblings ...)
2018-07-13 14:09 ` [platforms: PATCH 3/6] Marvell/Library: ComPhyLib: Configure RXAUI " Marcin Wojtas
@ 2018-07-13 14:09 ` Marcin Wojtas
2018-07-13 14:09 ` [platforms: PATCH 5/6] Marvell/Library: ComPhyLib: Clean up the library after rework Marcin Wojtas
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Marcin Wojtas @ 2018-07-13 14:09 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Replace the comphy initialization for USB with appropriate SMC call,
so the firmware will execute required serdes configuration.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 167 +-------------------
1 file changed, 4 insertions(+), 163 deletions(-)
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
index c46cad1..35ac459 100755
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
@@ -100,168 +100,6 @@ COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {
STATIC
VOID
-ComPhyUsb3RFUConfiguration (
- IN EFI_PHYSICAL_ADDRESS ComPhyAddr
-)
-{
- UINT32 Mask, Data;
-
- /* RFU configurations - hard reset ComPhy */
- Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
- Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
- Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
- Data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
- Mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
- Data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
- Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
- Data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
- Mask |= COMMON_PHY_PHY_MODE_MASK;
- Data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET;
- RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
-
- /* Release from hard reset */
- Mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
- Data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
- Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
- Data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
- RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
-
- /* Wait 1ms - until band gap and ref clock ready */
- MicroSecondDelay (1000);
- MemoryFence ();
-}
-
-STATIC
-VOID
-ComPhyUsb3PhyConfiguration (
- IN EFI_PHYSICAL_ADDRESS HpipeAddr
-)
-{
- UINT32 Mask, Data;
-
- /* Set PIPE soft reset */
- Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
- Data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
-
- /* Set PHY Datapath width mode for V0 */
- Mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
- Data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
-
- /* Set Data bus width USB mode for V0 */
- Mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
- Data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
-
- /* Set CORE_CLK output frequency for 250Mhz */
- Mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
- Data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
- RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask);
-
- /* Set PLL ready delay for 0x2 */
- RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG,
- 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
- HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
-
- /* Set reference clock to come from group 1 - 25Mhz */
- RegSet (HpipeAddr + HPIPE_MISC_REG, 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
- HPIPE_MISC_REFCLK_SEL_MASK);
-
- /* Set reference frequcency select - 0x2 */
- Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
- Data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
-
- /* Set PHY mode to USB - 0x5 */
- Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
- Data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
- RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
-
- /* Set the amount of time spent in the LoZ state - set for 0x7 */
- RegSet (HpipeAddr + HPIPE_GLOBAL_PM_CTRL,
- 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
- HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
-
- /* Set max PHY generation setting - 5Gbps */
- RegSet (HpipeAddr + HPIPE_INTERFACE_REG,
- 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, HPIPE_INTERFACE_GEN_MAX_MASK);
-
- /* Set select Data width 20Bit (SEL_BITS[2:0]) */
- RegSet (HpipeAddr + HPIPE_LOOPBACK_REG,
- 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
-}
-
-STATIC
-VOID
-ComPhyUsb3SetAnalogParameters (
- IN EFI_PHYSICAL_ADDRESS HpipeAddr
-)
-{
- UINT32 Data, Mask;
-
- /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */
- Mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK;
- Data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET;
-
- /* Set Override PHY DFE control pins for 0x1 */
- Mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK;
- Data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET;
-
- /* Set Spread Spectrum Clock Enable fot 0x1 */
- Mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
- Data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
- RegSet (HpipeAddr + HPIPE_LANE_CFG4_REG, Data, Mask);
-}
-
-STATIC
-UINTN
-ComphyUsb3PowerUp (
- UINT32 Lane,
- EFI_PHYSICAL_ADDRESS HpipeBase,
- EFI_PHYSICAL_ADDRESS ComPhyBase
- )
-{
- EFI_STATUS Status = EFI_SUCCESS;
- UINT32 Data;
- EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
- EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
-
- DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
-
- ComPhyUsb3RFUConfiguration (ComPhyAddr);
-
- /* Start ComPhy Configuration */
- DEBUG((DEBUG_INFO, "stage: Comphy configuration\n"));
-
- ComPhyUsb3PhyConfiguration (HpipeAddr);
-
- /* Start analog paramters from ETP(HW) */
- DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n"));
-
- ComPhyUsb3SetAnalogParameters (HpipeAddr);
-
- DEBUG((DEBUG_INFO, "ComPhy: stage: Comphy power up\n"));
-
- /* Release from PIPE soft reset */
- RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG,
- 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
- HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
-
- /* Wait 15ms - for ComPhy calibration done */
- MicroSecondDelay (15000);
- MemoryFence ();
-
- DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n"));
-
- /* Read Lane status */
- Data = MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG);
- if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) {
- DEBUG((DEBUG_ERROR, "ComPhy: HPIPE_LANE_STATUS0_PCLK_EN_MASK is 0\n"));
- Status = EFI_D_ERROR;
- }
-
- return Status;
-}
-
-STATIC
-VOID
ComPhySataMacPowerDown (
IN EFI_PHYSICAL_ADDRESS SataBase
)
@@ -528,7 +366,10 @@ ComPhyCp110Init (
break;
case COMPHY_TYPE_USB3_HOST0:
case COMPHY_TYPE_USB3_HOST1:
- Status = ComphyUsb3PowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr);
+ Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON,
+ PtrChipCfg->ComPhyBaseAddr,
+ Lane,
+ COMPHY_FW_MODE_FORMAT (COMPHY_USB3H_MODE));
break;
case COMPHY_TYPE_SGMII0:
case COMPHY_TYPE_SGMII1:
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [platforms: PATCH 5/6] Marvell/Library: ComPhyLib: Clean up the library after rework
2018-07-13 14:09 [platforms: PATCH 0/6] Armada7k8k ComPhy rework Marcin Wojtas
` (3 preceding siblings ...)
2018-07-13 14:09 ` [platforms: PATCH 4/6] Marvell/Library: ComPhyLib: Configure USB " Marcin Wojtas
@ 2018-07-13 14:09 ` Marcin Wojtas
2018-07-13 14:09 ` [platforms: PATCH 6/6] Marvell/Library: ComPhyLib: Remove both PHY and PIPE selector config Marcin Wojtas
2018-07-25 10:02 ` [platforms: PATCH 0/6] Armada7k8k ComPhy rework Ard Biesheuvel
6 siblings, 0 replies; 11+ messages in thread
From: Marcin Wojtas @ 2018-07-13 14:09 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Because all ComPhy related initialization was moved to ARM-TF
all register definitions and some related routines/structures became
unused. This commit removes them.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 488 --------------------
Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 28 --
2 files changed, 516 deletions(-)
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
index 972cbbb..4bb9c95 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
@@ -129,475 +129,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define COMPHY_FW_PCIE_FORMAT(pcie_width, mode, speeds) \
((pcie_width << 18) | COMPHY_FW_FORMAT (mode, 0, speeds))
-#define COMPHY_POLARITY_NO_INVERT 0
-#define COMPHY_POLARITY_TXD_INVERT 1
-#define COMPHY_POLARITY_RXD_INVERT 2
-#define COMPHY_POLARITY_ALL_INVERT (COMPHY_POLARITY_TXD_INVERT | COMPHY_POLARITY_RXD_INVERT)
-
-/***** SerDes IP registers *****/
-#define SD_EXTERNAL_CONFIG0_REG 0
-#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1
-#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11
-#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12
-#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14
-#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
-#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15
-#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
-
-#define SD_EXTERNAL_CONFIG1_REG 0x4
-#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3
-#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4
-#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5
-#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6
-#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
-
-#define SD_EXTERNAL_CONFIG2_REG 0x8
-#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
-#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
-#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7
-#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)
-
-#define SD_EXTERNAL_STATUS0_REG 0x18
-#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
-#define SD_EXTERNAL_STATUS0_PLL_TX_MASK (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
-#define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3
-#define SD_EXTERNAL_STATUS0_PLL_RX_MASK (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
-#define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4
-#define SD_EXTERNAL_STATUS0_RX_INIT_MASK (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
-
-/***** HPIPE registers *****/
-#define HPIPE_PWR_PLL_REG 0x4
-#define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0
-#define HPIPE_PWR_PLL_REF_FREQ_MASK (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
-#define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5
-#define HPIPE_PWR_PLL_PHY_MODE_MASK (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
-
-#define HPIPE_KVCO_CALIB_CTRL_REG 0x8
-#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12
-#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
-
-#define HPIPE_CAL_REG1_REG 0xc
-#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10
-#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
-#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15
-#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
-
-#define HPIPE_SQUELCH_FFE_SETTING_REG 0x018
-
-#define HPIPE_DFE_REG0 0x01C
-#define HPIPE_DFE_RES_FORCE_OFFSET 15
-#define HPIPE_DFE_RES_FORCE_MASK (0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
-
-#define HPIPE_DFE_F3_F5_REG 0x028
-#define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14
-#define HPIPE_DFE_F3_F5_DFE_EN_MASK (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
-#define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15
-#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
-
-#define HPIPE_G1_SET0_REG 0x034
-#define HPIPE_G2_SET0_REG 0x03c
-#define HPIPE_G3_SET0_REG 0x044
-#define HPIPE_GX_SET0_TX_AMP_OFFSET 1
-#define HPIPE_GX_SET0_TX_AMP_MASK (0x1f << HPIPE_GX_SET0_TX_AMP_OFFSET)
-#define HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET 6
-#define HPIPE_GX_SET0_TX_AMP_ADJ_MASK (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET)
-#define HPIPE_GX_SET0_TX_EMPH1_OFFSET 7
-#define HPIPE_GX_SET0_TX_EMPH1_MASK (0xf << HPIPE_GX_SET0_TX_EMPH1_OFFSET)
-#define HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET 11
-#define HPIPE_GX_SET0_TX_EMPH1_EN_MASK (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET)
-#define HPIPE_GX_SET0_TX_SLEW_RATE_SEL_OFFSET 12
-#define HPIPE_GX_SET0_TX_SLEW_RATE_SEL_MASK (0x7 << HPIPE_GX_SET0_TX_SLEW_RATE_SEL_OFFSET)
-#define HPIPE_GX_SET0_TX_SLEW_CTRL_EN_OFFSET 15
-#define HPIPE_GX_SET0_TX_SLEW_CTRL_EN_MASK (0x1 << HPIPE_GX_SET0_TX_SLEW_CTRL_EN_OFFSET)
-
-#define HPIPE_G1_SET1_REG 0x038
-#define HPIPE_G2_SET1_REG 0x040
-#define HPIPE_G3_SET1_REG 0x048
-#define HPIPE_GX_SET1_RX_SELMUPI_OFFSET 0
-#define HPIPE_GX_SET1_RX_SELMUPI_MASK (0x7 << HPIPE_GX_SET1_RX_SELMUPI_OFFSET)
-#define HPIPE_GX_SET1_RX_SELMUPP_OFFSET 3
-#define HPIPE_GX_SET1_RX_SELMUPP_MASK (0x7 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET)
-#define HPIPE_GX_SET1_RX_SELMUFI_OFFSET 6
-#define HPIPE_GX_SET1_RX_SELMUFI_MASK (0x3 << HPIPE_GX_SET1_RX_SELMUFI_OFFSET)
-#define HPIPE_GX_SET1_RX_SELMUFF_OFFSET 8
-#define HPIPE_GX_SET1_RX_SELMUFF_MASK (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET)
-#define HPIPE_GX_SET1_RX_DFE_EN_OFFSET 10
-#define HPIPE_GX_SET1_RX_DFE_EN_MASK (0x1 << HPIPE_GX_SET1_RX_DFE_EN_OFFSET)
-#define HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET 11
-#define HPIPE_GX_SET1_RX_DIGCK_DIV_MASK (0x3 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET)
-#define HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_OFFSET 13
-#define HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_MASK (0x1 << HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_OFFSET)
-
-#define HPIPE_LOOPBACK_REG 0x08c
-#define HPIPE_LOOPBACK_SEL_OFFSET 1
-#define HPIPE_LOOPBACK_SEL_MASK (0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
-
-#define HPIPE_SYNC_PATTERN_REG 0x090
-
-#define HPIPE_INTERFACE_REG 0x94
-#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
-#define HPIPE_INTERFACE_GEN_MAX_MASK (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
-#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12
-#define HPIPE_INTERFACE_DET_BYPASS_MASK (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET)
-#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
-#define HPIPE_INTERFACE_LINK_TRAIN_MASK (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
-
-#define HPIPE_ISOLATE_MODE_REG 0x98
-#define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0
-#define HPIPE_ISOLATE_MODE_GEN_RX_MASK (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET)
-#define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4
-#define HPIPE_ISOLATE_MODE_GEN_TX_MASK (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
-
-#define HPIPE_GX_SET2_REG 0xf4
-#define HPIPE_GX_SET2_TX_EMPH0_OFFSET 0
-#define HPIPE_GX_SET2_TX_EMPH0_MASK (0xf << HPIPE_GX_SET2_TX_EMPH0_OFFSET)
-#define HPIPE_GX_SET2_TX_EMPH0_EN_OFFSET 4
-#define HPIPE_GX_SET2_TX_EMPH0_EN_MASK (0x1 << HPIPE_GX_SET2_TX_EMPH0_MASK)
-
-#define HPIPE_VTHIMPCAL_CTRL_REG 0x104
-
-#define HPIPE_VDD_CAL_CTRL_REG 0x114
-#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5
-#define HPIPE_EXT_SELLV_RXSAMPL_MASK (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
-
-#define HPIPE_VDD_CAL_0_REG 0x108
-#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15
-#define HPIPE_CAL_VDD_CONT_MODE_MASK (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET)
-
-#define HPIPE_PCIE_REG0 0x120
-#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
-#define HPIPE_PCIE_IDLE_SYNC_MASK (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
-#define HPIPE_PCIE_SEL_BITS_OFFSET 13
-#define HPIPE_PCIE_SEL_BITS_MASK (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
-
-#define HPIPE_LANE_ALIGN_REG 0x124
-#define HPIPE_LANE_ALIGN_OFF_OFFSET 12
-#define HPIPE_LANE_ALIGN_OFF (0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET)
-#define HPIPE_LANE_ALIGN_OFF_MASK (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
-
-#define HPIPE_MISC_REG 0x13C
-#define HPIPE_MISC_CLK100M_125M_OFFSET 4
-#define HPIPE_MISC_CLK100M_125M_EN (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
-#define HPIPE_MISC_CLK100M_125M_MASK (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
-#define HPIPE_MISC_ICP_FORCE_OFFSET 5
-#define HPIPE_MISC_ICP_FORCE_MASK (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
-#define HPIPE_MISC_TXDCLK_2X_OFFSET 6
-#define HPIPE_MISC_TXDCLK_2X_500MHZ (0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET)
-#define HPIPE_MISC_TXDCLK_2X_MASK (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
-#define HPIPE_MISC_CLK500_EN_OFFSET 7
-#define HPIPE_MISC_CLK500_EN_MASK (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
-#define HPIPE_MISC_REFCLK_SEL_OFFSET 10
-#define HPIPE_MISC_REFCLK_SEL_MASK (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
-
-#define HPIPE_RX_CONTROL_1_REG 0x140
-#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11
-#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
-#define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12
-#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
-
-#define HPIPE_PWR_CTR_REG 0x148
-#define HPIPE_PWR_CTR_RST_DFE_OFFSET 0
-#define HPIPE_PWR_CTR_RST_DFE_MASK (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
-#define HPIPE_PWR_CTR_SFT_RST_OFFSET 10
-#define HPIPE_PWR_CTR_SFT_RST_MASK (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
-
-#define HPIPE_PLLINTP_REG1 0x150
-
-#define HPIPE_SPD_DIV_FORCE_REG 0x154
-#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7
-#define HPIPE_TXDIGCK_DIV_FORCE_MASK (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)
-
-#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
-#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6
-#define HPIPE_RX_SAMPLER_OS_GAIN_MASK (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET)
-#define HPIPE_SAMPLER_OFFSET 12
-#define HPIPE_SAMPLER_MASK (0x1 << HPIPE_SAMPLER_OFFSET)
-
-#define HPIPE_TX_REG1_REG 0x174
-#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5
-#define HPIPE_TX_REG1_TX_EMPH_RES_MASK (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
-#define HPIPE_TX_REG1_SLC_EN_OFFSET 10
-#define HPIPE_TX_REG1_SLC_EN_MASK (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
-
-#define HPIPE_TX_REG1_REG 0x174
-#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5
-#define HPIPE_TX_REG1_TX_EMPH_RES_MASK (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
-#define HPIPE_TX_REG1_SLC_EN_OFFSET 10
-#define HPIPE_TX_REG1_SLC_EN_MASK (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
-
-#define HPIPE_PWR_CTR_DTL_REG 0x184
-#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0
-#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1
-#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
-#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4
-#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET)
-#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10
-#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET)
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET)
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET)
-
-#define HPIPE_PHASE_CONTROL_REG 0x188
-#define HPIPE_OS_PH_OFFSET_OFFSET 0
-#define HPIPE_OS_PH_OFFSET_MASK (0x7f << HPIPE_OS_PH_OFFSET_OFFSET)
-#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7
-#define HPIPE_OS_PH_OFFSET_FORCE_MASK (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
-#define HPIPE_OS_PH_VALID_OFFSET 8
-#define HPIPE_OS_PH_VALID_MASK (0x1 << HPIPE_OS_PH_VALID_OFFSET)
-
-#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214
-#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7
-#define HPIPE_TRAIN_PAT_NUM_MASK (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET)
-
-#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220
-#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12
-#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET)
-
-#define HPIPE_DME_REG 0x228
-#define HPIPE_DME_ETHERNET_MODE_OFFSET 7
-#define HPIPE_DME_ETHERNET_MODE_MASK (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
-#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
-#define HPIPE_TX_TRAIN_P2P_HOLD_MASK (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_REG 0x26C
-#define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0
-#define HPIPE_TX_TRAIN_CTRL_G1_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
-#define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1
-#define HPIPE_TX_TRAIN_CTRL_GN1_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
-#define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2
-#define HPIPE_TX_TRAIN_CTRL_G0_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_4_REG 0x278
-#define HPIPE_TRX_TRAIN_TIMER_OFFSET 0
-#define HPIPE_TRX_TRAIN_TIMER_MASK (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
-
-#define HPIPE_PCIE_REG1 0x288
-#define HPIPE_PCIE_REG3 0x290
-
-#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
-#define HPIPE_RX_TRAIN_TIMER_OFFSET 0
-#define HPIPE_RX_TRAIN_TIMER_MASK (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET)
-#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11
-#define HPIPE_TX_TRAIN_START_SQ_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
-#define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12
-#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET)
-#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13
-#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET)
-#define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14
-#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
-
-#define HPIPE_TX_TRAIN_REG 0x31C
-#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4
-#define HPIPE_TX_TRAIN_CHK_INIT_MASK (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
-#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
-#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
-#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8
-#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET)
-#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9
-#define HPIPE_TX_TRAIN_PAT_SEL_MASK (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
-
-#define HPIPE_CDR_CONTROL_REG 0x418
-#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6
-#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
-#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
-#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
-#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
-#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
-#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
-#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
-#define HPIPE_TX_NUM_OF_PRESET_OFFSET 10
-#define HPIPE_TX_NUM_OF_PRESET_MASK (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
-#define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15
-#define HPIPE_TX_SWEEP_PRESET_EN_MASK (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
-
-#define HPIPE_G1_SET3_REG 0x440
-#define HPIPE_G2_SET3_REG 0x448
-#define HPIPE_G3_SET3_REG 0x450
-#define HPIPE_GX_SET3_FFE_CAP_SEL_OFFSET 0
-#define HPIPE_GX_SET3_FFE_CAP_SEL_MASK (0xf << HPIPE_GX_SET3_FFE_CAP_SEL_OFFSET)
-#define HPIPE_GX_SET3_FFE_RES_SEL_OFFSET 4
-#define HPIPE_GX_SET3_FFE_RES_SEL_MASK (0x7 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET)
-#define HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET 7
-#define HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK (0x1 << HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET)
-#define HPIPE_GX_SET3_FBCK_SEL_OFFSET 9
-#define HPIPE_GX_SET3_FBCK_SEL_MASK (0x1 << HPIPE_GX_SET3_FBCK_SEL_OFFSET)
-#define HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET 12
-#define HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK (0x3 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET)
-#define HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET 14
-#define HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK (0x3 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET)
-
-#define HPIPE_G1_SET4_REG 0x444
-#define HPIPE_G2_SET4_REG 0x44C
-#define HPIPE_G3_SET4_REG 0x454
-#define HPIPE_GX_SET4_DFE_RES_OFFSET 8
-#define HPIPE_GX_SET4_DFE_RES_MASK (0x3 << HPIPE_GX_SET4_DFE_RES_OFFSET)
-
-#define HPIPE_TX_PRESET_INDEX_REG 0x468
-#define HPIPE_TX_PRESET_INDEX_OFFSET 0
-#define HPIPE_TX_PRESET_INDEX_MASK (0xf << HPIPE_TX_PRESET_INDEX_OFFSET)
-
-#define HPIPE_DFE_CONTROL_REG 0x470
-#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14
-#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)
-
-#define HPIPE_DFE_CTRL_28_REG 0x49C
-#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
-#define HPIPE_DFE_CTRL_28_PIPE4_MASK (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
-
-#define HPIPE_G1_SET5_REG 0x538
-#define HPIPE_G3_SET5_REG 0x548
-#define HPIPE_GX_SET5_ICP_OFFSET 0
-#define HPIPE_GX_SET5_ICP_MASK (0xf << HPIPE_GX_SET5_ICP_OFFSET)
-
-#define HPIPE_LANE_CONFIG0_REG 0x604
-#define HPIPE_LANE_CONFIG0_MAX_PLL_OFFSET 9
-#define HPIPE_LANE_CONFIG0_MAX_PLL_MASK (0x1 << HPIPE_LANE_CONFIG0_MAX_PLL_OFFSET)
-#define HPIPE_LANE_CONFIG0_GEN2_PLL_OFFSET 10
-#define HPIPE_LANE_CONFIG0_GEN2_PLL_MASK (0x1 << HPIPE_LANE_CONFIG0_GEN2_PLL_OFFSET)
-
-#define HPIPE_LANE_STATUS0_REG 0x60C
-#define HPIPE_LANE_STATUS0_PCLK_EN_OFFSET 0
-#define HPIPE_LANE_STATUS0_PCLK_EN_MASK (0x1 << HPIPE_LANE_STATUS0_PCLK_EN_OFFSET)
-
-#define HPIPE_LANE_CFG4_REG 0x620
-#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
-#define HPIPE_LANE_CFG4_DFE_CTRL_MASK (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
-#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3
-#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
-#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
-#define HPIPE_LANE_CFG4_DFE_OVER_MASK (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
-#define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7
-#define HPIPE_LANE_CFG4_SSC_CTRL_MASK (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
-
-#define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C
-#define HPIPE_CFG_PHY_RC_EP_OFFSET 12
-#define HPIPE_CFG_PHY_RC_EP_MASK (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
-
-#define HPIPE_LANE_EQ_CFG1_REG 0x6a0
-#define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12
-#define HPIPE_CFG_UPDATE_POLARITY_MASK (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
-
-#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8
-#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0
-#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
-#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1
-#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
-#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2
-#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_DEFAULT (0x1 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
-#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
-
-#define HPIPE_RST_CLK_CTRL_REG 0x704
-#define HPIPE_RST_CLK_CTRL_CLR_ALL_MASK MAX_UINT32
-#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
-#define HPIPE_RST_CLK_CTRL_PIPE_RST_DISABLE (0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
-#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
-#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
-#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
-#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
-#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_16 (0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
-#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
-#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
-#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET 4
-#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_MASK (0x3 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
-#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_1 (0x0 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
-#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_2 (0x1 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
-#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_4 (0x2 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
-#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_8 (0x3 << HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET)
-#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
-#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
-
-#define HPIPE_CLK_SRC_LO_REG 0x70c
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_DEFAULT (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_DEFAULT (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
-#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
-#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_DEFAULT (0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
-#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
-
-#define HPIPE_CLK_SRC_HI_REG 0x710
-#define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
-#define HPIPE_CLK_SRC_HI_LANE_STRT_EN (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
-#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
-#define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
-#define HPIPE_CLK_SRC_HI_LANE_BREAK_EN (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
-#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
-#define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
-#define HPIPE_CLK_SRC_HI_LANE_MASTER_EN (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
-#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
-#define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
-#define HPIPE_CLK_SRC_HI_MODE_PIPE_EN (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
-#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
-
-#define HPIPE_GLOBAL_MISC_CTRL 0x718
-#define HPIPE_GLOBAL_PM_CTRL 0x740
-#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0
-#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
-
-/***** COMPHY registers *****/
-#define COMMON_PHY_CFG1_REG 0x0
-#define COMMON_PHY_CFG1_PWR_UP_OFFSET 1
-#define COMMON_PHY_CFG1_PWR_UP_MASK (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
-#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
-#define COMMON_PHY_CFG1_PIPE_SELECT_MASK (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
-#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13
-#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
-#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14
-#define COMMON_PHY_CFG1_CORE_RSTN_MASK (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
-#define COMMON_PHY_PHY_MODE_OFFSET 15
-#define COMMON_PHY_PHY_MODE_MASK (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
-
-#define COMMON_PHY_CFG6_REG 0x14
-#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
-#define COMMON_PHY_CFG6_IF_40_SEL_MASK (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
-
-#define COMMON_SELECTOR_PHY_OFFSET 0x140
-#define COMMON_SELECTOR_PIPE_OFFSET 0x144
-
-#define COMMON_PHY_SD_CTRL1 0x148
-#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
-#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_ENABLE 0x0
-#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_DISABLE 0x3210
-#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
-#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
-#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
-#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
-#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
-#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
-#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
-#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
-#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
-#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
-#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
-
/***** SATA registers *****/
#define SATA3_VENDOR_ADDRESS 0xA0
#define SATA3_VENDOR_ADDR_OFSSET 0
@@ -628,11 +159,6 @@ typedef struct {
} COMPHY_MUX_OPTIONS;
typedef struct {
- UINT32 MaxLaneValues;
- COMPHY_MUX_OPTIONS MuxValues[MAX_LANE_OPTIONS];
-} COMPHY_MUX_DATA;
-
-typedef struct {
UINT8 Type;
UINT8 Speed;
UINT8 Invert;
@@ -653,7 +179,6 @@ VOID
struct _CHIP_COMPHY_CONFIG {
MV_COMPHY_CHIP_TYPE ChipType;
COMPHY_MAP MapData[MAX_LANE_OPTIONS];
- COMPHY_MUX_DATA *MuxData;
EFI_PHYSICAL_ADDRESS ComPhyBaseAddr;
EFI_PHYSICAL_ADDRESS Hpipe3BaseAddr;
COMPHY_CHIP_INIT Init;
@@ -688,17 +213,4 @@ RegSetSilent (
IN UINT32 Mask
);
-VOID
-RegSet16 (
- IN EFI_PHYSICAL_ADDRESS Addr,
- IN UINT16 Data,
- IN UINT16 Mask
- );
-
-VOID
-RegSetSilent16(
- IN EFI_PHYSICAL_ADDRESS Addr,
- IN UINT16 Data,
- IN UINT16 Mask
- );
#endif // __COMPHY_H__
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
index b3a8c10..8e12894 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c
@@ -82,34 +82,6 @@ RegSetSilent (
MmioWrite32 (Addr, RegData);
}
-VOID
-RegSet16 (
- IN EFI_PHYSICAL_ADDRESS Addr,
- IN UINT16 Data,
- IN UINT16 Mask
- )
-{
- DEBUG((DEBUG_INFO, "Write to address = %#010lx, Data = %#06x (mask = %#06x)"
- "- ", Addr, Data, Mask));
- DEBUG((DEBUG_INFO, "old value = %#06x ==> ", MmioRead16 (Addr)));
- RegSetSilent16 (Addr, Data, Mask);
- DEBUG((DEBUG_INFO, "new value %#06x\n", MmioRead16 (Addr)));
-}
-
-VOID
-RegSetSilent16(
- IN EFI_PHYSICAL_ADDRESS Addr,
- IN UINT16 Data,
- IN UINT16 Mask
- )
-{
- UINT16 RegData;
- RegData = MmioRead16(Addr);
- RegData &= ~Mask;
- RegData |= Data;
- MmioWrite16 (Addr, RegData);
-}
-
CHAR16 *
GetTypeString (
UINT32 Type
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [platforms: PATCH 6/6] Marvell/Library: ComPhyLib: Remove both PHY and PIPE selector config
2018-07-13 14:09 [platforms: PATCH 0/6] Armada7k8k ComPhy rework Marcin Wojtas
` (4 preceding siblings ...)
2018-07-13 14:09 ` [platforms: PATCH 5/6] Marvell/Library: ComPhyLib: Clean up the library after rework Marcin Wojtas
@ 2018-07-13 14:09 ` Marcin Wojtas
2018-07-25 10:02 ` [platforms: PATCH 0/6] Armada7k8k ComPhy rework Ard Biesheuvel
6 siblings, 0 replies; 11+ messages in thread
From: Marcin Wojtas @ 2018-07-13 14:09 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, mw, jsd, jaz
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Now the ComPhy configuration is handled in ARM-TF, therefore there is no
need to configure PHY or PIPE selector in UEFI. Remove unused code.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 1 -
Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 7 --
Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 97 --------------
Silicon/Marvell/Library/ComPhyLib/ComPhyMux.c | 132 --------------------
4 files changed, 237 deletions(-)
delete mode 100644 Silicon/Marvell/Library/ComPhyLib/ComPhyMux.c
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
index 7a72203..36f498b 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
@@ -58,7 +58,6 @@
[Sources.common]
ComPhyLib.c
ComPhyCp110.c
- ComPhyMux.c
[Protocols]
gMarvellBoardDescProtocolGuid ## CONSUMES
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
index 4bb9c95..76d033d 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h
@@ -188,13 +188,6 @@ struct _CHIP_COMPHY_CONFIG {
};
VOID
-ComPhyMuxInit (
- IN CHIP_COMPHY_CONFIG *PtrChipCfg,
- IN COMPHY_MAP *ComPhyMapData,
- IN EFI_PHYSICAL_ADDRESS SelectorBase
- );
-
-VOID
ComPhyCp110Init (
IN CHIP_COMPHY_CONFIG * First
);
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
index 35ac459..2abb006 100755
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c
@@ -46,58 +46,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define HPIPE_ADDR(base, Lane) (SD_ADDR(base, Lane) + HPIPE_ADDR_OFFSET)
#define COMPHY_ADDR(base, Lane) (base + COMPHY_ADDR_LANE_WIDTH * Lane)
-/*
- * For CP-110 we have 2 Selector registers "PHY Selectors"
- * and " PIPE Selectors".
- * PIPE selector include USB and PCIe options.
- * PHY selector include the Ethernet and SATA options, every Ethernet option
- * has different options, for example: serdes Lane2 have option Eth_port_0
- * that include (SGMII0, RXAUI0, SFI)
- */
-COMPHY_MUX_DATA Cp110ComPhyMuxData[] = {
- /* Lane 0 */
- {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1},
- {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}},
- /* Lane 1 */
- {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},
- {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}},
- /* Lane 2 */
- {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1},
- {COMPHY_TYPE_RXAUI0, 0x1}, {COMPHY_TYPE_SFI, 0x1},
- {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}},
- /* Lane 3 */
- {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1},
- {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4},
- {COMPHY_TYPE_SATA3, 0x4}}},
- /* Lane 4 */
- {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2},
- {COMPHY_TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2},
- {COMPHY_TYPE_SGMII1, 0x1}}},
- /* Lane 5 */
- {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},
- {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4},
- {COMPHY_TYPE_SATA3, 0x4}}},
-};
-
-COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {
- /* Lane 0 */
- {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PCIE0, 0x4}}},
- /* Lane 1 */
- {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST0, 0x1},
- {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PCIE0, 0x4}}},
- /* Lane 2 */
- {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST0, 0x1},
- {COMPHY_TYPE_PCIE0, 0x4}}},
- /* Lane 3 */
- {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST1, 0x1},
- {COMPHY_TYPE_PCIE0, 0x4}}},
- /* Lane 4 */
- {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST1, 0x1},
- {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PCIE1, 0x4}}},
- /* Lane 5 */
- {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PCIE2, 0x4}}},
-};
-
STATIC
VOID
ComPhySataMacPowerDown (
@@ -240,48 +188,6 @@ ComPhySataPowerUp (
return Status;
}
-STATIC
-VOID
-ComPhyMuxCp110 (
- IN CHIP_COMPHY_CONFIG *PtrChipCfg,
- IN COMPHY_MAP *SerdesMap
- )
-{
- EFI_PHYSICAL_ADDRESS ComPhyBaseAddr;
- COMPHY_MAP ComPhyMapPipeData[MAX_LANE_OPTIONS];
- COMPHY_MAP ComPhyMapPhyData[MAX_LANE_OPTIONS];
- UINT32 Lane, ComPhyMaxCount;
-
- ComPhyMaxCount = PtrChipCfg->LanesCount;
- ComPhyBaseAddr = PtrChipCfg->ComPhyBaseAddr;
-
- /*
- * Copy the SerDes map configuration for PIPE map and PHY map.
- * The ComPhyMuxInit modifies the Type of the Lane if the Type is not valid.
- * Because we have 2 selectors, run the ComPhyMuxInit twice and after
- * that, update the original SerdesMap.
- */
- for (Lane = 0; Lane < ComPhyMaxCount; Lane++) {
- ComPhyMapPipeData[Lane].Type = SerdesMap[Lane].Type;
- ComPhyMapPipeData[Lane].Speed = SerdesMap[Lane].Speed;
- ComPhyMapPhyData[Lane].Type = SerdesMap[Lane].Type;
- ComPhyMapPhyData[Lane].Speed = SerdesMap[Lane].Speed;
- }
- PtrChipCfg->MuxData = Cp110ComPhyMuxData;
- ComPhyMuxInit(PtrChipCfg, ComPhyMapPhyData, ComPhyBaseAddr +
- COMMON_SELECTOR_PHY_OFFSET);
-
- PtrChipCfg->MuxData = Cp110ComPhyPipeMuxData;
- ComPhyMuxInit(PtrChipCfg, ComPhyMapPipeData, ComPhyBaseAddr +
- COMMON_SELECTOR_PIPE_OFFSET);
-
- /* Fix the Type after check the PHY and PIPE configuration */
- for (Lane = 0; Lane < ComPhyMaxCount; Lane++)
- if ((ComPhyMapPipeData[Lane].Type == COMPHY_TYPE_UNCONNECTED) &&
- (ComPhyMapPhyData[Lane].Type == COMPHY_TYPE_UNCONNECTED))
- SerdesMap[Lane].Type = COMPHY_TYPE_UNCONNECTED;
-}
-
VOID
ComPhyCp110Init (
IN CHIP_COMPHY_CONFIG *PtrChipCfg
@@ -302,9 +208,6 @@ ComPhyCp110Init (
SerdesMap = PtrChipCfg->MapData;
ChipId = PtrChipCfg->ChipId;
- /* Config Comphy mux configuration */
- ComPhyMuxCp110(PtrChipCfg, SerdesMap);
-
/* Check if the first 4 Lanes configured as By-4 */
for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < 4; Lane++, PtrComPhyMap++) {
if (PtrComPhyMap->Type != COMPHY_TYPE_PCIE0) {
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyMux.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyMux.c
deleted file mode 100644
index 6589fec..0000000
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyMux.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/********************************************************************************
-Copyright (C) 2016 Marvell International Ltd.
-
-Marvell BSD License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File under the following licensing terms.
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
-* Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
-* Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-#include "ComPhyLib.h"
-
-STATIC
-VOID
-ComPhyMuxCheckConfig (
- IN COMPHY_MUX_DATA *MuxData,
- IN COMPHY_MAP *ComPhyMapData,
- IN UINTN ComPhyMaxLanes
- )
-{
- COMPHY_MUX_OPTIONS *PtrMuxOpt;
- UINTN Lane, Opt, Valid;
-
- for (Lane = 0; Lane < ComPhyMaxLanes; Lane++, ComPhyMapData++, MuxData++) {
- PtrMuxOpt = MuxData->MuxValues;
- for (Opt = 0, Valid = 0; Opt < MuxData->MaxLaneValues; Opt++, PtrMuxOpt++) {
- if (PtrMuxOpt->Type == ComPhyMapData->Type) {
- Valid = 1;
- break;
- }
- }
- if (Valid == 0) {
- DEBUG((DEBUG_INFO, "Lane number %d, had invalid Type %d\n", Lane,
- ComPhyMapData->Type));
- DEBUG((DEBUG_INFO, "Set Lane %d as Type %d\n", Lane,
- COMPHY_TYPE_UNCONNECTED));
- ComPhyMapData->Type = COMPHY_TYPE_UNCONNECTED;
- } else {
- DEBUG((DEBUG_INFO, "Lane number %d, has Type %d\n", Lane,
- ComPhyMapData->Type));
- }
- }
-}
-
-STATIC
-UINT32
-ComPhyMuxGetMuxValue (
- IN COMPHY_MUX_DATA *MuxData,
- IN UINT32 Type,
- IN UINTN Lane
- )
-{
- COMPHY_MUX_OPTIONS *PtrMuxOpt;
- UINTN Opt;
- UINT32 Value = 0;
-
- PtrMuxOpt = MuxData->MuxValues;
- for (Opt = 0 ; Opt < MuxData->MaxLaneValues; Opt++, PtrMuxOpt++)
- if (PtrMuxOpt->Type == Type) {
- Value = PtrMuxOpt->MuxValue;
- break;
- }
-
- return Value;
-}
-
-STATIC
-VOID
-ComPhyMuxRegWrite (
- IN COMPHY_MUX_DATA *MuxData,
- IN COMPHY_MAP *ComPhyMapData,
- IN UINTN ComPhyMaxLanes,
- IN EFI_PHYSICAL_ADDRESS SelectorBase,
- IN UINT32 BitCount
- )
-{
- UINT32 Lane, Value, Offset, Mask;
-
- for (Lane = 0; Lane < ComPhyMaxLanes; Lane++, ComPhyMapData++, MuxData++) {
- Offset = Lane * BitCount;
- Mask = (((1 << BitCount) - 1) << Offset);
- Value = (ComPhyMuxGetMuxValue (MuxData, ComPhyMapData->Type, Lane) <<
- Offset);
- RegSet (SelectorBase, Value, Mask);
- }
-}
-
-VOID
-ComPhyMuxInit (
- IN CHIP_COMPHY_CONFIG *PtrChipCfg,
- IN COMPHY_MAP *ComPhyMapData,
- IN EFI_PHYSICAL_ADDRESS SelectorBase
- )
-{
- COMPHY_MUX_DATA *MuxData;
- UINT32 MuxBitCount;
- UINT32 ComPhyMaxLanes;
-
- ComPhyMaxLanes = PtrChipCfg->LanesCount;
- MuxData = PtrChipCfg->MuxData;
- MuxBitCount = PtrChipCfg->MuxBitCount;
-
- /* Check if the configuration is valid */
- ComPhyMuxCheckConfig (MuxData, ComPhyMapData, ComPhyMaxLanes);
- /* Init COMPHY selectors */
- ComPhyMuxRegWrite (MuxData, ComPhyMapData, ComPhyMaxLanes, SelectorBase,
- MuxBitCount);
-}
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [platforms: PATCH 0/6] Armada7k8k ComPhy rework
2018-07-13 14:09 [platforms: PATCH 0/6] Armada7k8k ComPhy rework Marcin Wojtas
` (5 preceding siblings ...)
2018-07-13 14:09 ` [platforms: PATCH 6/6] Marvell/Library: ComPhyLib: Remove both PHY and PIPE selector config Marcin Wojtas
@ 2018-07-25 10:02 ` Ard Biesheuvel
6 siblings, 0 replies; 11+ messages in thread
From: Ard Biesheuvel @ 2018-07-25 10:02 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel@lists.01.org, Leif Lindholm, Nadav Haklai,
Jan Dąbroś, Grzegorz Jaszczyk
On 13 July 2018 at 16:09, Marcin Wojtas <mw@semihalf.com> wrote:
> Hi,
>
> This patchset makes use of the feature present in newest,
> publicly available ARM-TF of the Armada7k8k SoCs
> (https://github.com/MarvellEmbeddedProcessors/atf-marvell/commits/atf-v1.4-armada-18.06)
> which is a common configuration of the serdes lanes.
>
> It is triggered by the users (UEFI/U-Boot/OS) using
> the dedicated smc calls. Thanks to that the library
> could have been cleaned-up and reduced to the per-board
> configuration parsing part and calling the according
> sequences to be done in EL3.
>
> The patches are available in the github:
> https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/comphy-upstream-r20180713
>
> I'm looking forward to review and any comments/remarks.
>
> Best regards,
> Marcin
>
> Grzegorz Jaszczyk (6):
> Marvell/Library: ComPhyLib: Configure SATA, SGMII and SFI in ARM-TF
> Marvell/Library: ComPhyLib: Configure PCIE in ARM-TF
> Marvell/Library: ComPhyLib: Configure RXAUI in ARM-TF
> Marvell/Library: ComPhyLib: Configure USB in ARM-TF
> Marvell/Library: ComPhyLib: Clean up the library after rework
> Marvell/Library: ComPhyLib: Remove both PHY and PIPE selector config
>
This looks fine except for the remarks I made in reply to patches #1 and #2
> Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 18 +-
> Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 2 +-
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.h | 22 -
> Silicon/Marvell/Include/Library/SampleAtResetLib.h | 7 -
> Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 545 +-----
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.c | 19 -
> Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 1777 +-------------------
> Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 41 +-
> Silicon/Marvell/Library/ComPhyLib/ComPhyMux.c | 132 --
> 9 files changed, 116 insertions(+), 2447 deletions(-)
> delete mode 100644 Silicon/Marvell/Library/ComPhyLib/ComPhyMux.c
>
> --
> 2.7.4
>
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