From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::244; helo=mail-io0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x244.google.com (mail-io0-x244.google.com [IPv6:2607:f8b0:4001:c06::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 356BB21CEB142 for ; Thu, 26 Oct 2017 08:08:36 -0700 (PDT) Received: by mail-io0-x244.google.com with SMTP id i38so6104788iod.2 for ; Thu, 26 Oct 2017 08:12:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=DvS1Ut+hrpB2MnIWvxecgqEp2MY95b/gSMzjcCLm4UA=; b=UdfPOcVkS/+goa3nkhoaPphyMccltRtfb1IRTqq68uIcwBXxQu3cuVFZqBDTJ8YsIP sBWnqOO+nnJzdN2fADDvkNjfVf7Pe7FkfTtQb+KlsptiDvwhxj9g6aDV0QH99JirhaSc tdjot2YLpBdnJwmfg02PKDtoXiI5EHWHSmrqo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=DvS1Ut+hrpB2MnIWvxecgqEp2MY95b/gSMzjcCLm4UA=; b=Xo3CtpnOQ0hs84S5w4LGqJs7rhzSLk/6WVs83ikENJ9UmYa7rRzKcAyoc0r7VSfxtZ 6MgSnJOG4JbXWaVGp4xs+NSEvT0iNCRjDLS8eHXZUnKtZpG8c1ovcmsZ105PufEGnRbv e0lk0aR4fHtPlxqxhhtxk4eQWJ+yOA39w8ZHjnn2Iz9n0CPyjDgoPgChIm2cvKFZHCJ+ rPmdwP8aRO6SHlWQqFXgzhVVc7O72wIsGS26DagG+6D50YzGzePhmL7yRRgVyFc5DAIY Us/+kCiNJwCaVh7BQWDSAnaQ8E2prDVfaCNutYnMJWo03Co9z4ePjoSN3l8eFlaIFASt iutQ== X-Gm-Message-State: AMCzsaW45+ZNruy+bOboOb49CaSGKV4hOEYFkqFiYq2XzvqZ36ryyIWy JgKcRlKqpcnj2h/VKy/hhhR+f7EAwcvhV1xdt1KWxQ== X-Google-Smtp-Source: ABhQp+R6udkknDnivfcQk/f25Bx63AFRk4H6aiAA8BNWsY8hE0vcdrHOl6pGetuzilPfeWxe2/DVfz5OziLPMl+wP50= X-Received: by 10.36.254.140 with SMTP id w134mr2931172ith.73.1509030741555; Thu, 26 Oct 2017 08:12:21 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.131.167 with HTTP; Thu, 26 Oct 2017 08:12:21 -0700 (PDT) In-Reply-To: <20171026151027.p6er7jcvjcsrmthq@bivouac.eciton.net> References: <20171025175947.22798-1-ard.biesheuvel@linaro.org> <20171025175947.22798-7-ard.biesheuvel@linaro.org> <20171026151027.p6er7jcvjcsrmthq@bivouac.eciton.net> From: Ard Biesheuvel Date: Thu, 26 Oct 2017 16:12:21 +0100 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Daniel Thompson , Masami Hiramatsu Subject: Re: [PATCH edk2-platforms v2 06/23] Silicon/SynQuacer: implement PciHostBridgeLib support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 15:08:36 -0000 Content-Type: text/plain; charset="UTF-8" On 26 October 2017 at 16:10, Leif Lindholm wrote: > On Wed, Oct 25, 2017 at 06:59:30PM +0100, Ard Biesheuvel wrote: >> Implement the glue library that exposes the PCIe root complexes to >> the generic PCI host bridge driver. Since that driver is the first >> one to access the PCI config space, put the low level init code for >> the RCs into this library's constructor. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel >> --- >> Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 220 +++++++++++ >> Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 50 +++ >> Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 388 ++++++++++++++++++++ >> 3 files changed, 658 insertions(+) >> >> diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c >> new file mode 100644 >> index 000000000000..3937e98c0213 >> --- /dev/null >> +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c >> @@ -0,0 +1,220 @@ >> +/** @file >> + PCI Host Bridge Library instance for Socionext SynQuacer ARM SOC >> + >> + Copyright (c) 2017, Linaro Ltd. All rights reserved.
>> + >> + This program and the accompanying materials are licensed and made available >> + under the terms and conditions of the BSD License which accompanies this >> + distribution. The full text of the license may be found at >> + http://opensource.org/licenses/bsd-license.php. >> + >> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT >> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. >> + >> +**/ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#pragma pack(1) >> +typedef struct { >> + ACPI_HID_DEVICE_PATH AcpiDevicePath; >> + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; >> +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; >> +#pragma pack () >> + >> +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { >> + { >> + { >> + { >> + ACPI_DEVICE_PATH, >> + ACPI_DP, >> + { >> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), >> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) >> + } >> + }, >> + EISA_PNP_ID (0x0A08), // PCI Express >> + 0 >> + }, >> + >> + { >> + END_DEVICE_PATH_TYPE, >> + END_ENTIRE_DEVICE_PATH_SUBTYPE, >> + { >> + END_DEVICE_PATH_LENGTH, >> + 0 >> + } >> + } >> + }, >> + { >> + { >> + { >> + ACPI_DEVICE_PATH, >> + ACPI_DP, >> + { >> + (UINT8)(sizeof(ACPI_HID_DEVICE_PATH)), >> + (UINT8)(sizeof(ACPI_HID_DEVICE_PATH) >> 8) >> + } >> + }, >> + EISA_PNP_ID (0x0A08), // PCI Express >> + 1 >> + }, >> + >> + { >> + END_DEVICE_PATH_TYPE, >> + END_ENTIRE_DEVICE_PATH_SUBTYPE, >> + { >> + END_DEVICE_PATH_LENGTH, >> + 0 >> + } >> + } >> + } >> +}; >> + >> +GLOBAL_REMOVE_IF_UNREFERENCED >> +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { >> + L"Mem", L"I/O", L"Bus" >> +}; >> + >> +STATIC PCI_ROOT_BRIDGE mPciRootBridges[] = { >> + { >> + 0, // Segment >> + 0, // Supports >> + 0, // Attributes >> + TRUE, // DmaAbove4G >> + FALSE, // NoExtendedConfigSpace >> + FALSE, // ResourceAssigned >> + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | >> + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, // AllocationAttributes >> + { SYNQUACER_PCI_SEG0_BUSNUM_MIN, >> + SYNQUACER_PCI_SEG0_BUSNUM_MAX }, // Bus >> + { SYNQUACER_PCI_SEG0_PORTIO_MIN, >> + SYNQUACER_PCI_SEG0_PORTIO_MAX }, // Io >> + { SYNQUACER_PCI_SEG0_MMIO32_MIN, >> + SYNQUACER_PCI_SEG0_MMIO32_MAX }, // Mem >> + { SYNQUACER_PCI_SEG0_MMIO64_MIN, >> + SYNQUACER_PCI_SEG0_MMIO64_MAX }, // MemAbove4G >> + { MAX_UINT64, 0x0 }, // PMem >> + { MAX_UINT64, 0x0 }, // PMemAbove4G >> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] >> + }, { >> + 1, // Segment >> + 0, // Supports >> + 0, // Attributes >> + TRUE, // DmaAbove4G >> + FALSE, // NoExtendedConfigSpace >> + FALSE, // ResourceAssigned >> + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | >> + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, // AllocationAttributes >> + { SYNQUACER_PCI_SEG1_BUSNUM_MIN, >> + SYNQUACER_PCI_SEG1_BUSNUM_MAX }, // Bus >> + { SYNQUACER_PCI_SEG1_PORTIO_MIN, >> + SYNQUACER_PCI_SEG1_PORTIO_MAX }, // Io >> + { SYNQUACER_PCI_SEG1_MMIO32_MIN, >> + SYNQUACER_PCI_SEG1_MMIO32_MAX }, // Mem >> + { SYNQUACER_PCI_SEG1_MMIO64_MIN, >> + SYNQUACER_PCI_SEG1_MMIO64_MAX }, // MemAbove4G >> + { MAX_UINT64, 0x0 }, // PMem >> + { MAX_UINT64, 0x0 }, // PMemAbove4G >> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1] >> + } >> +}; >> + >> +/** >> + Return all the root bridge instances in an array. >> + >> + @param Count Return the count of root bridge instances. >> + >> + @return All the root bridge instances in an array. >> + The array should be passed into PciHostBridgeFreeRootBridges() >> + when it's not used. >> +**/ >> +PCI_ROOT_BRIDGE * >> +EFIAPI >> +PciHostBridgeGetRootBridges ( >> + OUT UINTN *Count >> + ) >> +{ >> + *Count = ARRAY_SIZE (mPciRootBridges); >> + >> + return mPciRootBridges; >> +} >> + >> +/** >> + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). >> + >> + @param Bridges The root bridge instances array. >> + @param Count The count of the array. >> +**/ >> +VOID >> +EFIAPI >> +PciHostBridgeFreeRootBridges ( >> + PCI_ROOT_BRIDGE *Bridges, >> + UINTN Count >> + ) >> +{ >> +} >> + >> +/** >> + Inform the platform that the resource conflict happens. >> + >> + @param HostBridgeHandle Handle of the Host Bridge. >> + @param Configuration Pointer to PCI I/O and PCI memory resource >> + descriptors. The Configuration contains the resources >> + for all the root bridges. The resource for each root >> + bridge is terminated with END descriptor and an >> + additional END is appended indicating the end of the >> + entire resources. The resource descriptor field >> + values follow the description in >> + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL >> + .SubmitResources(). >> +**/ >> +VOID >> +EFIAPI >> +PciHostBridgeResourceConflict ( >> + EFI_HANDLE HostBridgeHandle, >> + VOID *Configuration >> + ) >> +{ >> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; >> + UINTN RootBridgeIndex; >> + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); >> + >> + RootBridgeIndex = 0; >> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; >> + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { >> + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); >> + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { >> + ASSERT (Descriptor->ResType < >> + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)); >> + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", >> + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], >> + Descriptor->AddrLen, Descriptor->AddrRangeMax >> + )); >> + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { >> + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", >> + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, >> + ((Descriptor->SpecificFlag & >> + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE >> + ) != 0) ? L" (Prefetchable)" : L"" >> + )); >> + } >> + } >> + // >> + // Skip the END descriptor for root bridge >> + // >> + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); >> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( >> + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 >> + ); >> + } >> +} >> diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf >> new file mode 100644 >> index 000000000000..fca62b2577da >> --- /dev/null >> +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf >> @@ -0,0 +1,50 @@ >> +## @file >> +# PCI Host Bridge Library instance for Socionext SynQuacer ARM SOC >> +# >> +# Copyright (c) 2017, Linaro Ltd. All rights reserved.
>> +# >> +# This program and the accompanying materials are licensed and made available >> +# under the terms and conditions of the BSD License which accompanies this >> +# distribution. The full text of the license may be found at >> +# http://opensource.org/licenses/bsd-license.php >> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR >> +# IMPLIED. >> +# >> +# >> +## >> + >> +[Defines] >> + INF_VERSION = 0x00010019 >> + BASE_NAME = SynQuacerPciHostBridgeLib >> + FILE_GUID = fdc92446-65bc-4f86-b4a0-014a2119a732 >> + MODULE_TYPE = DXE_DRIVER >> + VERSION_STRING = 1.0 >> + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER >> + CONSTRUCTOR = SynQuacerPciHostBridgeLibConstructor >> + >> +# >> +# The following information is for reference only and not required by the build >> +# tools. >> +# >> +# VALID_ARCHITECTURES = AARCH64 > > So, this is still marked as AARCH64-only, even though the platform is > marked |ARM? > Ah yes. This code needs to be modified to omit the MMIO64 regions, given that ARM cannot accesses those in a 1:1 mapped address space. Mind if I use MDE_CPU_xxx ifdefs for that?