From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::232; helo=mail-it0-x232.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x232.google.com (mail-it0-x232.google.com [IPv6:2607:f8b0:4001:c0b::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3A87A203564B2 for ; Tue, 28 Nov 2017 06:18:12 -0800 (PST) Received: by mail-it0-x232.google.com with SMTP id m191so1181818itg.2 for ; Tue, 28 Nov 2017 06:22:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=aOsvaoG4/TXYHzaUoDOUgJwz+ogRpD/MfL4QIHHtHrQ=; b=QQqhZDEreuGcsMScTQ+rv4VC2hE2kQm3tHQ1VaGSKNKbqPO2EaV5cWL8M5leSiiSqm Qm0D4F5fxRWXvu5BwdDpc22t2J3fg4K+njoA6rAJc+vlel8+5byXCP1Nt40CFCJF9G8W 8qFFDOut4okRKFfhl9blSdH5xkCfK1MdJXxmg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=aOsvaoG4/TXYHzaUoDOUgJwz+ogRpD/MfL4QIHHtHrQ=; b=SXEFfqkmlqxm7NRcGiyNzLCsiN9YSyF69BkN4kFGnz0SzQCPPDDEL5Gu+kSzcewdTo LDCJAUyphTPlZCp9YpVI3TzU+DDsHNAc0Hk9v71Uiok5yeJzjFJb2z+y+OICDw/fCmpz 4V4YicIGpyBNpw2UjYgsydWvI/sBGhOFmcw5U32uQa+snVvDYjFHHXxaGvJ7yf/Geu5g S/3Y5IRa+LweyeTlCJf2PWD4gVtfRhSo7bTMYFQIXRz/p1fO476C+0xcgtcxHCK17N7K J7UKfasAhvUJXu2GPrlPCHCLe/UoZpmv481Za7JlSo1FYaWg9O/UZ1X6aocwGaavHAdi 8Maw== X-Gm-Message-State: AJaThX65uZdzvScmDsJcvo2scFCgftVqKMVWv3MsCOKX5vEBYPlLEN2e zGGHa3iHYS89/T+tyRL33e0lIPx7j2kwM/h7729GEw== X-Google-Smtp-Source: AGs4zMa8PBWptYtSzq+EJQcJRfN8r1cc93iRK9r8sl1jW5s4e8kNJoG9zJyEAroa23Q+ZEdNXM5Qfz2enBCBrbF0vGM= X-Received: by 10.36.31.212 with SMTP id d203mr2532116itd.48.1511878954542; Tue, 28 Nov 2017 06:22:34 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.104.16 with HTTP; Tue, 28 Nov 2017 06:22:34 -0800 (PST) In-Reply-To: <20171128141954.6drhx3avq7hwlch2@bivouac.eciton.net> References: <20171128132807.16701-1-ard.biesheuvel@linaro.org> <20171128134951.ah5rkkes5wx6leu6@bivouac.eciton.net> <20171128141954.6drhx3avq7hwlch2@bivouac.eciton.net> From: Ard Biesheuvel Date: Tue, 28 Nov 2017 14:22:34 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Daniel Thompson , masahisa.kojima@socionext.com, =?UTF-8?B?UGlwYXQv44Oh44K/44Ov44OL44OD44OI44Od44OzIOODlOODkeODg+ODiA==?= Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Nov 2017 14:18:12 -0000 Content-Type: text/plain; charset="UTF-8" On 28 November 2017 at 14:19, Leif Lindholm wrote: > On Tue, Nov 28, 2017 at 01:53:49PM +0000, Ard Biesheuvel wrote: >> On 28 November 2017 at 13:49, Leif Lindholm wrote: >> > On Tue, Nov 28, 2017 at 01:37:20PM +0000, Ard Biesheuvel wrote: >> >> On 28 November 2017 at 13:28, Ard Biesheuvel wrote: >> >> > As it turns out, it is surprisingly easy to configure both the NETSEC >> >> > and eMMC devices as cache coherent for DMA, given that they are both >> >> > behind the same SMMU which is already configured in passthrough mode. >> > >> > Configures in passthrough mode by edk2 or earlier firmware? >> >> No, it is the CM3 firmware that configures the various SMMUs on this platform. > > Right, could you add that to the above statement please? > "... already configured in passthrough mode by the CM3 firmware."? > OK >> >> > So update the static SMMU configuration to make memory accesses performed >> >> > by these devices inner shareable, inner/outer writeback cacheable, which >> >> > makes them cache coherent with the CPUs. >> >> > >> >> > Contributed-under: TianoCore Contribution Agreement 1.1 >> >> > Signed-off-by: Ard Biesheuvel >> >> > --- >> >> > Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 2 +- >> >> > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 ++ >> >> > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 2 +- >> >> > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 23 ++++++++++++++++++++ >> >> > Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++++ >> >> > Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 3 +++ >> >> > 6 files changed, 34 insertions(+), 2 deletions(-) >> >> > >> >> > diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc >> >> > index 7245240012bc..dd4a7f9baf69 100644 >> >> > --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc >> >> > +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc >> >> > @@ -597,7 +597,7 @@ [Components.common] >> >> > NetworkPkg/HttpBootDxe/HttpBootDxe.inf >> >> > Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf { >> >> > >> >> > - DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf >> >> > + DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf >> >> > } >> >> > >> >> > # >> >> >> >> Note: this hunk ^^^ needs to be applied to DeveloperBox.dsc as well. >> > >> > Do I wait for a v2 including that? >> > >> >> Would you like me to? > > No, I was just wondering. > Does the .dtsi change not cause issues for DeveloperBox without it? > Yes, it does, hence the need to apply this hunk to DeveloperBox.dsc as well. >> I added this for Daniel and/or Masami, in case they were intending to >> test this patch. I'd like to get confirmation from them or others that >> this works as expected before merging this, so there is no rush. > > Right, thanks. > > / > Leif