From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::143; helo=mail-it1-x143.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it1-x143.google.com (mail-it1-x143.google.com [IPv6:2607:f8b0:4864:20::143]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D5BBB21A07A92 for ; Mon, 14 Jan 2019 09:52:20 -0800 (PST) Received: by mail-it1-x143.google.com with SMTP id h65so629429ith.3 for ; Mon, 14 Jan 2019 09:52:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ZiU5BkfLyst9WWUH1qkdFE5p7l5wIvYxUiK4QH07GpM=; b=WsQ7rpsucqRqH4YUjS0PFE2oS7JTo+zHA4vzbExmwXPBi/AFAIgkYZtCg6nm+hPMZu eWkDilB5QKKtvuIdLfLR6gxUz7x/6kAo1TcwcgNuDABVhkqqNMBhtucnQ3vVTaJb649/ LNaE19WWz3VzFIi1mYe/DBMRjaK+7CNQUbBbY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ZiU5BkfLyst9WWUH1qkdFE5p7l5wIvYxUiK4QH07GpM=; b=dGnLywKZo/TpNaxuQFOu36pz/xrZ7EKvrIhvBH8o/0Gk/P2jYmYdvte8pMypM2wCo5 LuJVtQNlOnUnw/IKS333XhPxBsRX32oMe+9MMDLNvR+wFr5M5MXBKaDKLYh/4HlUWnAM zp5/wimPqgdjg0dCX5w5hhuXTm5DzQwKJfEdg/nIOpphilSv3yMLJ3EeSkONOC428wQS OxerGAnaCy+sk629SsKUOKrd+R8AnwUMqTb8t68YbieAoNj6A3pK56Lr/7LZYNGrXhsn dueT/TcVt0pdbqi+2yZZ78KKcuBHbwBXI8S5YqW0BN3m2zbCbWAjw5NYr9sg4mNIS7ze l1Mg== X-Gm-Message-State: AJcUukdKBZ69RCDwrgHw/OaXkGPm2XZ7oTfgwPAD/SqJsL/yh/Z4NsnI jAm+4kKu9u7HiYQczO6lXdnh/fcOiJxQBBdtA8BRpLyp4Ro= X-Google-Smtp-Source: ALg8bN6kfBH8LENQTCJFu4udw2njg2cVTjTc0WewyRXoNMQrdrOHjz7r68SK98w+QoSFQufh+GKUB0DTFL/sfxH0YyM= X-Received: by 2002:a05:660c:4b:: with SMTP id p11mr195790itk.71.1547488338695; Mon, 14 Jan 2019 09:52:18 -0800 (PST) MIME-Version: 1.0 References: <20190114170205.9748-1-ard.biesheuvel@linaro.org> <20190114170205.9748-7-ard.biesheuvel@linaro.org> In-Reply-To: <20190114170205.9748-7-ard.biesheuvel@linaro.org> From: Ard Biesheuvel Date: Mon, 14 Jan 2019 18:52:07 +0100 Message-ID: To: "edk2-devel@lists.01.org" Subject: Re: [PATCH edk2-platforms 6/8] Silicon/SynQuacer/Stage2Tables: fix 32-bit build X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Jan 2019 17:52:21 -0000 Content-Type: text/plain; charset="UTF-8" On Mon, 14 Jan 2019 at 18:02, Ard Biesheuvel wrote: > > The static stage2 page tables don't contain any code, but we are > relying on the linker to resolve the references to the next level > tables, so we can only use native word size quantities. So add a > CPP macro to emit the same quantity in different ways. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 12 +++++++++--- The 'elf64-little' in the .inf is now wrong as well, but it seems I can just remove that and objcopy will detect the input format. > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S > index af55f27bca47..28c7a6ac970f 100644 > --- a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S > +++ b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S > @@ -32,6 +32,12 @@ > #define TT_S2_L3_PAGE (0x1 << 1) > #define TT_S2_VALID (0x1 << 0) > > +#ifdef __aarch64__ > +#define QWORD(x) .quad (x) > +#else > +#define QWORD(x) .long (x), 0 > +#endif > + > .altmacro > .macro for, start, count, do, arg2, arg3, arg4 > .if \count == 1 > @@ -69,7 +75,7 @@ > .section ".rodata", "a", %progbits > /* level 1 */ > s2_mem_entry 0 /* 0x0000_0000 - 0x3fff_ffff */ > - .quad 1f + TT_S2_TABLE /* 0x4000_0000 - 0x7fff_ffff */ > + QWORD (1f + TT_S2_TABLE) /* 0x4000_0000 - 0x7fff_ffff */ > for 2, 246, s2_mem_entry /* 0x8000_0000 - 0x3d_ffff_ffff */ > for 248, 8, s2_dev_entry /* PCIe MMIO64 */ > for 256, 768, s2_mem_entry /* 0x40_0000_0000 - 0xff_ffff_ffff */ > @@ -77,12 +83,12 @@ > /* level 2 */ > 1:for 0, 256, s2_mem_entry, 21, 0x40000000, 1 > > - .quad 2f + TT_S2_TABLE /* 0x6000_0000 -> RC #0 bus 0 */ > + QWORD (2f + TT_S2_TABLE) /* 0x6000_0000 -> RC #0 bus 0 */ > for 1, 15, s2_mem_entry, 21, 0x60000000 > for 0, 48, s2_mem_entry, 21, 0x62000000, 1 > for 0, 64, s2_dev_entry, 21, 0x68000000, 1 /* PCIe MMIO32 */ > > - .quad 3f + TT_S2_TABLE /* 0x7000_0000 -> RC #1 bus 0 */ > + QWORD (3f + TT_S2_TABLE) /* 0x7000_0000 -> RC #1 bus 0 */ > for 1, 15, s2_mem_entry, 21, 0x70000000 > for 0, 48, s2_mem_entry, 21, 0x72000000, 1 > for 0, 64, s2_dev_entry, 21, 0x78000000, 1 /* PCIe MMIO32 */ > -- > 2.17.1 >