From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::244; helo=mail-it0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x244.google.com (mail-it0-x244.google.com [IPv6:2607:f8b0:4001:c0b::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 074F521B02845 for ; Wed, 27 Jun 2018 00:26:05 -0700 (PDT) Received: by mail-it0-x244.google.com with SMTP id u4-v6so6050800itg.0 for ; Wed, 27 Jun 2018 00:26:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=wmlIcjEg/fh6lM/oaeNLPvJnXUkHTbOikIh5tGHHSa0=; b=Kg2UjfNhNkvgvYWVLIy6BPU9DRXCS+giygi7cxXymfL6o497tQvbglqxfl796Mi/IJ 89BVQ8AgnuR8H9uJYIwe9yWXRpgIDd4BqRQg6HrsGtN/Q8KvH10/zQgZF/49IbwM+Ca6 QE0+0jgVhVjX3d8cbQvTPy4p3q9DSyItHYqxg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=wmlIcjEg/fh6lM/oaeNLPvJnXUkHTbOikIh5tGHHSa0=; b=jEs/ECKfHXuMjWqRRCQ8X899hzkWREfQFUnRvVrfYD9LFi3jj3OT7NDONrxpzB8t4A MNT0KnLoKiC58orXvmmOYGa3nhHH82ESx7/DzEADtDWunD99vApJ8sDmOFGV/N1WFDt9 HXJvbMmjOsShUYPpmff+WSEipBEtOzvQfIxzJc0RX62kxHDltRzOovQWzOR658QB3qhB nOGVvwzLHVf4aUk9wIFmtjNe1HNifLGU+gfj/pJvH4Eg36v75gjGr9bfAmgxL7aRg84E jVS4Jwi6nUAn4jutNOEIQJOLQYGqwvdoWEXUZSQiA3vUMxgUCNcDXVPl607u7UfOM235 dXRg== X-Gm-Message-State: APt69E16QdH9ONX2WlI66lEzwSZSe+CdT/fizvMOxePHk5wIYynAsDzd FSwBv/ILvL3RQhz95JJviilYHIL9ra824Zs1+R+qXea6 X-Google-Smtp-Source: AAOMgpfaZSGHLib93ctZ82mLIA/6DzApTbvg+B8nWQmHbdt8OQJHNpC5gSUPxoOuHP9gslfMND4gJte0hLNR086OZUk= X-Received: by 2002:a02:6001:: with SMTP id i1-v6mr4073408jac.5.1530084364949; Wed, 27 Jun 2018 00:26:04 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:bbc7:0:0:0:0:0 with HTTP; Wed, 27 Jun 2018 00:26:04 -0700 (PDT) In-Reply-To: <20180627070443.42886-3-ming.huang@linaro.org> References: <20180627070443.42886-1-ming.huang@linaro.org> <20180627070443.42886-3-ming.huang@linaro.org> From: Ard Biesheuvel Date: Wed, 27 Jun 2018 09:26:04 +0200 Message-ID: To: Ming Huang Cc: Leif Lindholm , linaro-uefi , "edk2-devel@lists.01.org" , Graeme Gregory , guoheyi@huawei.com, wanghuiqiang , huangming , Jason Zhang , huangdaode@hisilicon.com, John Garry , Heyi Guo Subject: Re: [PATCH edk2-platforms v1 2/6] Hisilicon/D03/D05: Correct ATU Cfg0/Cfg1 base address X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jun 2018 07:26:06 -0000 Content-Type: text/plain; charset="UTF-8" On 27 June 2018 at 09:04, Ming Huang wrote: > From: Jason Zhang > > 1. During test PCIe mcs9922 UART card, the card can't > work because the IO ATU config is overlap by Cfg0/Cfg1 > ATU address. > 2. After adjust the ATU windows, Cfg0/Cfg1 config as below: > Cfg0 is equal to "ECAM + (BusBase, 0, 0)" > Cfg1 is equal to "ECAM + (BusBase + 2, 0, 0)" > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Jason Zhang > Signed-off-by: Heyi Guo > Signed-off-by: Ming Huang > --- > Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) > > diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c > index 55b80aa4e4..e5f66eaa4a 100644 > --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c > +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c > @@ -640,11 +640,12 @@ void SetAtuConfig0RW ( > { > UINTN RbPciBase = Private->RbPciBar; > UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1; > + UINT64 Cfg0Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0, 0, 0); > OK, so here you are mapping bus 0 ... > > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg0Base)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg0Base >> 32)); > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); > @@ -666,12 +667,12 @@ void SetAtuConfig1RW ( > { > UINTN RbPciBase = Private->RbPciBar; > UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1; > - > + UINT64 Cfg1Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0); and here you are mapping bus 2 .. buslimit. Where are you mapping bus 1? > > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg1Base)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg1Base >> 32)); > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); > -- > 2.17.0 >