From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::d44; helo=mail-io1-xd44.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd44.google.com (mail-io1-xd44.google.com [IPv6:2607:f8b0:4864:20::d44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 797C821A07A92 for ; Wed, 23 Jan 2019 07:55:40 -0800 (PST) Received: by mail-io1-xd44.google.com with SMTP id f4so2041219ion.2 for ; Wed, 23 Jan 2019 07:55:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=9TY2k1K46A6ida8oqPcJqNyBEOiEVzaHFp6x9XfsnsQ=; b=I9Tv55lCDPhgMrfbi0jwDIci0zxJuu8KaSA8WPf8TMQEQ2Amh583v1iWYa9a9Zo9xE 1OkHmFYy7qNqrF771X+Oc/KO7H1GqPjCCkNU3PHuVJctp9Ho9KmDoZ3+KUuZkaSEWoqS cq9EvVvpgBKmv5RJkP9UEAEgNdwqSbpQO6K4g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=9TY2k1K46A6ida8oqPcJqNyBEOiEVzaHFp6x9XfsnsQ=; b=LKaOwoGyPEueEdKvSNEeQNPYktvOXAdbkN6SMJF6CQGuc76hVDo4HEPrehcTKGLd+e Nj735nA07y0BrG4QE/n/DBpF/tnOkRYleWbrxsc7aB4cdX1O6I9FuVqQ8S33F5wpWVQd ExkT1lDcs18pRRL7870eujeTAKdZBw4tNWirHaqnv2Cdl0CzzV/4C6ZEGftIWIaDDIC8 5CSVfcKMK62O8RAOM24USGy4sCOYQMtup9bjs1iNzpIeply+QJ1XhZcYNXdTg5seyFU+ sF5CO/c43nR6VZaAkbvNM8cmAPmII3M6sDlvBX3ExN1LxVfuEAIypgaGu2k4c/Hi2kUa gvYg== X-Gm-Message-State: AHQUAuacVjD+fbc2KhQF2UJgfg300pTyM1ZZXboRYdendYRwrhY2LDqc yNPQtNrWV/ZhEsXEXBoET+UTbPop/kl/MntynAT51h/+wuI= X-Google-Smtp-Source: ALg8bN4++al4EXJfHZf7GO4aSq+dNPe9y1cWBKCAz94BTBzTA6hEYHUY99jG0onbq3jLyGmKTNsjB2qo/Gu9K8/aCPM= X-Received: by 2002:a5d:8410:: with SMTP id i16mr1512574ion.173.1548258939758; Wed, 23 Jan 2019 07:55:39 -0800 (PST) MIME-Version: 1.0 References: <20190107071504.2431-1-ard.biesheuvel@linaro.org> <20190107071504.2431-3-ard.biesheuvel@linaro.org> <20190123154622.pibw6mi5gh6ywb26@bivouac.eciton.net> In-Reply-To: <20190123154622.pibw6mi5gh6ywb26@bivouac.eciton.net> From: Ard Biesheuvel Date: Wed, 23 Jan 2019 16:55:28 +0100 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" Subject: Re: [PATCH 2/5] ArmPkg/ArmMmuLib AARCH64: get rid of needless TLB invalidation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Jan 2019 15:55:40 -0000 Content-Type: text/plain; charset="UTF-8" On Wed, 23 Jan 2019 at 16:46, Leif Lindholm wrote: > > On Mon, Jan 07, 2019 at 08:15:01AM +0100, Ard Biesheuvel wrote: > > Currently, we always invalidate the TLBs entirely after making > > any modification to the page tables. Now that we have introduced > > strict memory permissions in quite a number of places, such > > modifications occur much more often, and it is better for performance > > to flush only those TLB entries that are actually affected by > > the changes. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Ard Biesheuvel > > --- > > ArmPkg/Include/Library/ArmMmuLib.h | 3 ++- > > ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 6 +++--- > > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 16 +++++++--------- > > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S | 14 ++++++++------ > > 4 files changed, 20 insertions(+), 19 deletions(-) > > > > diff --git a/ArmPkg/Include/Library/ArmMmuLib.h b/ArmPkg/Include/Library/ArmMmuLib.h > > index fb7fd006417c..d2725810f1c6 100644 > > --- a/ArmPkg/Include/Library/ArmMmuLib.h > > +++ b/ArmPkg/Include/Library/ArmMmuLib.h > > @@ -59,7 +59,8 @@ VOID > > EFIAPI > > ArmReplaceLiveTranslationEntry ( > > IN UINT64 *Entry, > > - IN UINT64 Value > > + IN UINT64 Value, > > + IN UINT64 Address > > ); > > > > EFI_STATUS > > diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > > index b7173e00b039..175fb58206b6 100644 > > --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > > +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > > @@ -124,15 +124,15 @@ ASM_FUNC(ArmSetMAIR) > > // IN VOID *MVA // X1 > > // ); > > ASM_FUNC(ArmUpdateTranslationTableEntry) > > - dc civac, x0 // Clean and invalidate data line > > - dsb sy > > + dsb nshst > > + lsr x1, x1, #12 > > EL1_OR_EL2_OR_EL3(x0) > > 1: tlbi vaae1, x1 // TLB Invalidate VA , EL1 > > b 4f > > 2: tlbi vae2, x1 // TLB Invalidate VA , EL2 > > b 4f > > 3: tlbi vae3, x1 // TLB Invalidate VA , EL3 > > -4: dsb sy > > +4: dsb nsh > > isb > > ret > > > > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > > index d66df3e17a02..e1fabfcbea14 100644 > > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > > @@ -129,13 +129,14 @@ STATIC > > VOID > > ReplaceLiveEntry ( > > IN UINT64 *Entry, > > - IN UINT64 Value > > + IN UINT64 Value, > > + IN UINT64 Address > > ) > > { > > if (!ArmMmuEnabled ()) { > > *Entry = Value; > > } else { > > - ArmReplaceLiveTranslationEntry (Entry, Value); > > + ArmReplaceLiveTranslationEntry (Entry, Value, Address); > > } > > } > > > > @@ -296,7 +297,8 @@ GetBlockEntryListFromAddress ( > > > > // Fill the BlockEntry with the new TranslationTable > > ReplaceLiveEntry (BlockEntry, > > - ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes | TT_TYPE_TABLE_ENTRY); > > + (UINTN)TranslationTable | TableAttributes | TT_TYPE_TABLE_ENTRY, > > + RegionStart); > /me pages in the data ... > OK, this whole patch took a few times around the loop before I think I > caught on what was happening. > > I think I'm down to the only things confusing me being: > - The name "Address" to refer to something that is always the start > address of a 4KB-aligned translation region. > Is this because the function will be usable in other contexts in > later patches? I could change it to VirtualAddress if you prefer. It is only passed for TLB maintenance which is only needed at page granularity, and the low bits are shifted out anyway. > - Why drop the & TT_ADDRESS_MASK_DESCRIPTION_TABLE bit here? > Was it just always pointless and you decided to drop it while you > were at it? > IIRC yes. It is a newly allocated page, so the masking does not do anything. > / > Leif > > > } > > } else { > > if (IndexLevel != PageLevel) { > > @@ -375,6 +377,8 @@ UpdateRegionMapping ( > > *BlockEntry &= BlockEntryMask; > > *BlockEntry |= (RegionStart & TT_ADDRESS_MASK_BLOCK_ENTRY) | Attributes | Type; > > > > + ArmUpdateTranslationTableEntry (BlockEntry, (VOID *)RegionStart); > > + > > // Go to the next BlockEntry > > RegionStart += BlockEntrySize; > > RegionLength -= BlockEntrySize; > > @@ -487,9 +491,6 @@ ArmSetMemoryAttributes ( > > return Status; > > } > > > > - // Invalidate all TLB entries so changes are synced > > - ArmInvalidateTlb (); > > - > > return EFI_SUCCESS; > > } > > > > @@ -512,9 +513,6 @@ SetMemoryRegionAttribute ( > > return Status; > > } > > > > - // Invalidate all TLB entries so changes are synced > > - ArmInvalidateTlb (); > > - > > return EFI_SUCCESS; > > } > > > > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S > > index 90192df24f55..d40c19b2e3e5 100644 > > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S > > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S > > @@ -32,11 +32,12 @@ > > dmb sy > > dc ivac, x0 > > > > - // flush the TLBs > > + // flush translations for the target address from the TLBs > > + lsr x2, x2, #12 > > .if \el == 1 > > - tlbi vmalle1 > > + tlbi vaae1, x2 > > .else > > - tlbi alle\el > > + tlbi vae\el, x2 > > .endif > > dsb sy > > > > @@ -48,12 +49,13 @@ > > //VOID > > //ArmReplaceLiveTranslationEntry ( > > // IN UINT64 *Entry, > > -// IN UINT64 Value > > +// IN UINT64 Value, > > +// IN UINT64 Address > > // ) > > ASM_FUNC(ArmReplaceLiveTranslationEntry) > > > > // disable interrupts > > - mrs x2, daif > > + mrs x4, daif > > msr daifset, #0xf > > isb > > > > @@ -69,7 +71,7 @@ ASM_FUNC(ArmReplaceLiveTranslationEntry) > > b 4f > > 3:__replace_entry 3 > > > > -4:msr daif, x2 > > +4:msr daif, x4 > > ret > > > > ASM_GLOBAL ASM_PFX(ArmReplaceLiveTranslationEntrySize) > > -- > > 2.20.1 > >