From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::242; helo=mail-it0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x242.google.com (mail-it0-x242.google.com [IPv6:2607:f8b0:4001:c0b::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F1532211DB41C for ; Wed, 13 Jun 2018 00:19:02 -0700 (PDT) Received: by mail-it0-x242.google.com with SMTP id l6-v6so2557907iti.2 for ; Wed, 13 Jun 2018 00:19:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=/fPDQNgLuTRhp9L5Xuv4EwqpUiVqbETdhrm7wl8PkG8=; b=hvMSJVu5aRQo35b8iLLK0lVn2B2QU21+Apd5j5/McaQ7w5qspTaVY6XXxoH4sQ9win opxvi1MkNxooKyEXJpfHn51EXSCI9Hr9MsVNBoyGwjddjnmcGoi/HFOdCBFXU+Iqz963 4vcS/3FRWiPFukRh2IRdXfZYxAdkqF9Mwu59U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=/fPDQNgLuTRhp9L5Xuv4EwqpUiVqbETdhrm7wl8PkG8=; b=n0KBkA/o/d7BR+94uQznbdUCrdrQeXT+v55oBZIAsTw24BGmZwfaNR0eXB25IRIOUj 9N+Ld3dIT/ZrGnAdcXy5nfMlm4SNtDIdT99G88NjvKyvOP9CwJpghlTmlKCbofXZVWwx Z4qoTWG83FUiy3sHa7FGuLLcMGs5R+yQxzRwl9en9UXD9MxHWikTgTOP6MyaHIlVLTa4 HleZp/g/k9yI0a6GpDOt9tawNGRSstWfHn5yNciQSh+abqupgsZRZpp8zLAYXAc7vv4S lgHkEJLb8fqQNelLE/hhSMn8/2bQ66n88m4e2aswPuBVuVUhMbjirNYA3636h05Vr0wb MqYw== X-Gm-Message-State: APt69E1GSopTtFFYVpbpigUk5dblWF2hNYB/C9lCcawKyT8j/beANvcG SrdLcZBZzkSyjan2RCw9Co0InN5PXDSjCqT6einV061r3n4= X-Google-Smtp-Source: ADUXVKJ+XBZU46u064iZG//PDkZAzz2TdETaYVDGdmQkZFtvLTM8GLn0PiD4F0BmSVQ0MwLgl73GQsLvw44FjRAOQ2E= X-Received: by 2002:a24:3105:: with SMTP id y5-v6mr3618431ity.138.1528874342320; Wed, 13 Jun 2018 00:19:02 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:bbc7:0:0:0:0:0 with HTTP; Wed, 13 Jun 2018 00:19:01 -0700 (PDT) In-Reply-To: <20180612225919.kroissnk2tusdw76@bivouac.eciton.net> References: <20180607150818.14393-1-ard.biesheuvel@linaro.org> <20180607150818.14393-3-ard.biesheuvel@linaro.org> <20180612225919.kroissnk2tusdw76@bivouac.eciton.net> From: Ard Biesheuvel Date: Wed, 13 Jun 2018 09:19:01 +0200 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" Subject: Re: [PATCH edk2-platforms 2/2] Silicon/NorFlashSynQuacerLib: describe entire firmware region as FV X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jun 2018 07:19:03 -0000 Content-Type: text/plain; charset="UTF-8" On 13 June 2018 at 00:59, Leif Lindholm wrote: > On Thu, Jun 07, 2018 at 05:08:18PM +0200, Ard Biesheuvel wrote: >> In order to allow for more flexibility when updating parts of the >> firmware via capsule update, expand the description of the code FV >> to cover the entire 4 MB region at the base of the NOR flash. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel >> --- >> Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c | 5 +++-- >> 1 file changed, 3 insertions(+), 2 deletions(-) >> >> diff --git a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c >> index 816d8ba33f8c..357082c3d903 100644 >> --- a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c >> +++ b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c >> @@ -23,8 +23,9 @@ STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = { >> { >> // UEFI code region >> SYNQUACER_SPI_NOR_BASE, // device base >> - FixedPcdGet64 (PcdFdBaseAddress), // region base >> - FixedPcdGet32 (PcdFdSize), // region size >> + SYNQUACER_SPI_NOR_BASE, // region base >> + FixedPcdGet32 (PcdFlashNvStorageVariableBase) - >> + SYNQUACER_SPI_NOR_BASE, // region size > > Could you define the size as a macro in Platform/MemoryMap.h? > The memory map currently only contains constant macros. I can add this expression FixedPcdGet32 (PcdFlashNvStorageVariableBase) - SYNQUACER_SPI_NOR_BASE somewhere as a #define but I would prefer it to be elsewhere, given that it is not a SoC constant set in stone.