From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::244; helo=mail-io0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x244.google.com (mail-io0-x244.google.com [IPv6:2607:f8b0:4001:c06::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 96CD62034A88C for ; Fri, 27 Oct 2017 05:45:13 -0700 (PDT) Received: by mail-io0-x244.google.com with SMTP id m16so12451652iod.1 for ; Fri, 27 Oct 2017 05:49:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=4OLYH+HyD5grAwwCOFrgHfu4H5XD7utRrPGGMBz01UU=; b=Do7j4DutvCX/1BFoTmTHCENjcAGEgdBM3eUrIgy1gERqpNZRn+MNciK7iUcq7zgjtq cs25WwK1C2viuvVaVXoPE4DnjBHwAfm3riZ/unyQawZFX/ooy1VA0cKe4j+VsrBRavuE iqtoqxGPN8opBw2fyiGBO8YIiwtXxaCsyR4hc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=4OLYH+HyD5grAwwCOFrgHfu4H5XD7utRrPGGMBz01UU=; b=k/9zeenExmJjbukjlrUhj1MP3zYAk61ZwjHBaChfk2eAot8iw3OiZVqR+TatmwrTJN IbEeTrhtPbm4pi1ySODaHF0lHR6BQgElIlF6J9Dyb6+vMQlEzWwCJboEX842y3yNXMM+ lgE/U9lM/H0AQ5nserFZKinMOeHQAsFdjQW9j4ytm80nR99p9mJ4X3KQPXF4PwGT35RK qaMfcMJj0k2VxA77imGLtlpE9ZUymmMF5JWQJAUxpYjlFeUUn7ZBPsu3xZJbetFIdNYn dkLdv9Vvdghabyapmt87lvm9s0H/3I6S8m9isvQfoQ2uNYJS5gvQWVu31ur21LX7bkXI 4vTw== X-Gm-Message-State: AMCzsaXjP5MLM7HsPanLtw9aXQOfKRFL1GkCdC3B8e2Keys+PaXe+9OC SHU3+f0h3jDNgTx4zQHBmmwzTv7ggFwGg7n5Yp5Lg4dg X-Google-Smtp-Source: ABhQp+TOcP6npkudegDRNEgnRh/nmfpMIHqE1YbJ8OlzQQiIxWyvapw4odxR5O7ptVbwfpJpM7/fE37atGsGeuZwY34= X-Received: by 10.107.174.234 with SMTP id n103mr429620ioo.43.1509108540074; Fri, 27 Oct 2017 05:49:00 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.131.167 with HTTP; Fri, 27 Oct 2017 05:48:59 -0700 (PDT) In-Reply-To: <20171027053326.48815-1-daniil.egranov@arm.com> References: <20171027053326.48815-1-daniil.egranov@arm.com> From: Ard Biesheuvel Date: Fri, 27 Oct 2017 13:48:59 +0100 Message-ID: To: Daniil Egranov Cc: "edk2-devel@lists.01.org" , Leif Lindholm Subject: Re: [PATCH 0/4] SataSiI3132Dxe fixes X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2017 12:45:13 -0000 Content-Type: text/plain; charset="UTF-8" On 27 October 2017 at 06:33, Daniil Egranov wrote: > This set of patches fixes an issue with 64-bit DMA and implements > the missing exit boot event and driver stop functionality including > memory/protocols cleanup procedure. > > Daniil Egranov (4): > Drivers/SataSiI3132Dxe: Fixed PCI IO read and write operations > Drivers/SataSiI3132Dxe: Allow 64-bit DMA transfer > Drivers/SataSiI3132Dxe: Enable multi-controller support > Drivers/SataSiI3132Dxe: Fixed startup and shutdown procedures > > EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.c | 301 ++++++++++++++++----- > EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h | 17 ++ > .../Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c | 4 +- > 3 files changed, 252 insertions(+), 70 deletions(-) > Hi Daniil, Thanks for taking the time to fix this driver. I will go ahead and push the first two patches, given that they are self-contained and obvious bug fixes. The remaining patches, please split them up, and please align more closely with what other upstream PCI drivers do. Regards, Ard.