From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=cVM24yoU; spf=pass (domain: linaro.org, ip: 209.85.166.66, mailfrom: ard.biesheuvel@linaro.org) Received: from mail-io1-f66.google.com (mail-io1-f66.google.com [209.85.166.66]) by groups.io with SMTP; Thu, 16 May 2019 01:00:39 -0700 Received: by mail-io1-f66.google.com with SMTP id v7so1815461iob.10 for ; Thu, 16 May 2019 01:00:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=a74N09Ao1AIJc4SPB4o5OM+8n3stZPscWzUu7P+UgWY=; b=cVM24yoUrtG3t9D2GY1eqpLoPL4FJdZ47Rs/H1XB0GHEKzEjS2WLxpi97z8HkEE2Zu bdNFAGntXoIkuP6Xmrd4hF2rhgvEX53bxI1mfOYnFwDcEbdEPZ06wD1VhWxYSD6p2hSA xq4EQHbQKsw1uKj69Y6vGMzISHYpID6YxEuF3biMacWkOZpazWJXHjr+GMCNX9xe5Yk9 ts3jJNgCVcp/h5Kbj10hYbrEUiS4lghzEKkcpBj5I8flPrYHfYtE6gFj7EiWWStewzoe wDUuhP3borqnmLhNb4qZM0WAm8X/R4lwTbtIUY0i81B1/9Ud3DoVRGqPRPRU7LOoAP+P HRwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=a74N09Ao1AIJc4SPB4o5OM+8n3stZPscWzUu7P+UgWY=; b=k4f98ysU3jGqoM84FO0HhaZtiG3qQjBS4P6Y+lfvmfHsehu6r6f/+ih9Zptz/kSmEa SNmiFY7HfIl6M1Qgk3P4xwfi2o2tNTbr/TvKIYYlZAnAFrdVEg8af9w5cXlFTQCwHWMc bI97KCs+2fkHiXCtOlKcYOYFxCW6ufu3LMdxyF3/Oo1jxJhfX91USgZnyW9QgxSa+T0x WQ7nZk49BlH7ngJMowPuXJEbSUsas1XffZhdolBCsFHUtTVspgjG49Ms73f3NAM2k9tu XXwc0CqtHzufVn9PFubwRAx1HCdRe6yOfKi9Q1EQ6a74oCo20qqtqiWZ+JwSk6PmcQk+ pQjQ== X-Gm-Message-State: APjAAAVXKn/WOLrKHOTtaXs8uy+zqemNVBbeaIv2lvys/hFEIb8X6vKZ hUPVnGEzRQ6FxCnTxv9oOwrlgsczTWW2gEWkhmsyLlV3ZlrfaA== X-Google-Smtp-Source: APXvYqw90Mrjm1Nr/il3CtvT+Zsp1y4Ti109Q/nmxOM62CZVLDIm1kBEbHRf9SqQ6aGhGAsnX/fe1Sp/RjRPipnfjHo= X-Received: by 2002:a5d:93da:: with SMTP id j26mr26499721ioo.170.1557993638301; Thu, 16 May 2019 01:00:38 -0700 (PDT) MIME-Version: 1.0 References: <20190504000716.7525-1-lersek@redhat.com> <20190504000716.7525-4-lersek@redhat.com> In-Reply-To: <20190504000716.7525-4-lersek@redhat.com> From: "Ard Biesheuvel" Date: Thu, 16 May 2019 10:00:25 +0200 Message-ID: Subject: Re: [edk2-devel] [PATCH 3/4] OvmfPkg/PlatformPei: reorder the 32-bit PCI hole vs. the PCIEXBAR on q35 To: edk2-devel-groups-io , Laszlo Ersek Cc: Gerd Hoffmann , Jordan Justen Content-Type: text/plain; charset="UTF-8" On Sat, 4 May 2019 at 02:07, Laszlo Ersek wrote: > > Commit 7b8fe63561b4 ("OvmfPkg: PlatformPei: enable PCIEXBAR (aka MMCONFIG > / ECAM) on Q35", 2016-03-10) claimed that, > > On Q35 machine types that QEMU intends to support in the long term, QEMU > never lets the RAM below 4 GB exceed 2 GB. > > Alas, this statement came from a misunderstanding that occurred while we > worked out the interface contract. In fact QEMU does allow the 32-bit RAM > extend up to 0xB000_0000 (exclusive), in case the RAM size falls in the > range (0x8000_0000, 0xB000_0000) (i.e., the RAM size is greater than > 2048MB and smaller than 2816MB). > > In turn, such a RAM size (justifiedly) triggers > > ASSERT (TopOfLowRam <= PciExBarBase); > > in MemMapInitialization(), because we placed the 256MB PCIEXBAR at > 0x8000_0000 (2GB) exactly, relying on the interface contract. (And, the > 32-bit PCI hole would follow the PCIEXBAR, covering the [0x9000_0000, > 0xFC00_0000) range.) > > In order to fix this, reorder the 32-bit PCI hole against the PCIEXBAR, as > follows: > > - start the 32-bit PCI hole where it starts on i440fx as well, that is, at > 2GB or TopOfLowRam, whichever is higher; > > - unlike on i440fx, where the 32-bit PCI hole extends up to 0xFC00_0000, > stop it at 0xE000_0000 on q35, > > - place the PCIEXBAR at 0xE000_0000. > > (We cannot place the PCIEXBAR at 0xF000_0000 because the 256MB MMIO area > that starts there is not entirely free.) > > Before this patch, the 32-bit PCI hole used to only *end* at the same spot > (namely, 0xFC00_0000) between i440fx and q35; now it will only *start* at > the same spot (namely, 2GB or TopOfLowRam, whichever is higher) between > both boards. > > On q35, the maximal hole shrinks from > > 0xFC00_0000 - 0x9000_0000 = 0x6C00_0000 == 1728 MB > > to > > 0xE000_0000 - 0x8000_0000 == 1536 MB. > > We lose 192 MB of the aperture; however, the aperture is now aligned at > 1GB, rather than 256 MB, and so it could fit a 1GB BAR even. > > Regarding the minimal hole (triggered by RAM size 2815MB), its size is > > 0xE000_0000 - 0xAFF0_0000 = 769 MB > > which is not great, but probably better than a failed ASSERT. > > Cc: Ard Biesheuvel > Cc: Gerd Hoffmann > Cc: Jordan Justen > Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1666941 > Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1701710 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Laszlo Ersek I take it the 32-bit PCI 'hole' is in fact the 32-bit MMIO BAR window? That could do with a clarification. I guess it may be an x86-ism to consider any physical memory region not used by RAM to be a hole, but it is not terribly helpful. In any case, Reviewed-by: Ard Biesheuvel > --- > OvmfPkg/OvmfPkgIa32.dsc | 5 +---- > OvmfPkg/OvmfPkgIa32X64.dsc | 5 +---- > OvmfPkg/OvmfPkgX64.dsc | 5 +---- > OvmfPkg/PlatformPei/Platform.c | 9 ++++----- > 4 files changed, 7 insertions(+), 17 deletions(-) > > diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc > index 36a0f87258dd..bb55b6fa58e1 100644 > --- a/OvmfPkg/OvmfPkgIa32.dsc > +++ b/OvmfPkg/OvmfPkgIa32.dsc > @@ -491,10 +491,7 @@ [PcdsFixedAtBuild] > # This PCD is used to set the base address of the PCI express hierarchy. It > # is only consulted when OVMF runs on Q35. In that case it is programmed into > # the PCIEXBAR register. > - # > - # On Q35 machine types that QEMU intends to support in the long term, QEMU > - # never lets the RAM below 4 GB exceed 2 GB. > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 > > !ifdef $(SOURCE_DEBUG_ENABLE) > gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 > diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc > index 9b341e17d7ff..06c394a6fb1f 100644 > --- a/OvmfPkg/OvmfPkgIa32X64.dsc > +++ b/OvmfPkg/OvmfPkgIa32X64.dsc > @@ -496,10 +496,7 @@ [PcdsFixedAtBuild] > # This PCD is used to set the base address of the PCI express hierarchy. It > # is only consulted when OVMF runs on Q35. In that case it is programmed into > # the PCIEXBAR register. > - # > - # On Q35 machine types that QEMU intends to support in the long term, QEMU > - # never lets the RAM below 4 GB exceed 2 GB. > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 > > !ifdef $(SOURCE_DEBUG_ENABLE) > gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 > diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc > index a0f87f74dab9..5e0eb043fab9 100644 > --- a/OvmfPkg/OvmfPkgX64.dsc > +++ b/OvmfPkg/OvmfPkgX64.dsc > @@ -496,10 +496,7 @@ [PcdsFixedAtBuild] > # This PCD is used to set the base address of the PCI express hierarchy. It > # is only consulted when OVMF runs on Q35. In that case it is programmed into > # the PCIEXBAR register. > - # > - # On Q35 machine types that QEMU intends to support in the long term, QEMU > - # never lets the RAM below 4 GB exceed 2 GB. > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 > > !ifdef $(SOURCE_DEBUG_ENABLE) > gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 > diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c > index 9c013613a1a0..fd8eccaf3e50 100644 > --- a/OvmfPkg/PlatformPei/Platform.c > +++ b/OvmfPkg/PlatformPei/Platform.c > @@ -184,14 +184,13 @@ MemMapInitialization ( > PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; > if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { > // > - // The MMCONFIG area is expected to fall between the top of low RAM and > - // the base of the 32-bit PCI host aperture. > + // The 32-bit PCI host aperture is expected to fall between the top of > + // low RAM and the base of the MMCONFIG area. > // > PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress); > - ASSERT (TopOfLowRam <= PciExBarBase); > + ASSERT (PciBase < PciExBarBase); > ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB); > - PciBase = (UINT32)(PciExBarBase + SIZE_256MB); > - PciSize = 0xFC000000 - PciBase; > + PciSize = (UINT32)(PciExBarBase - PciBase); > } else { > PciSize = 0xFC000000 - PciBase; > } > -- > 2.19.1.3.g30247aa5d201 > > > > ------------ > Groups.io Links: You receive all messages sent to this group. > > View/Reply Online (#39968): https://edk2.groups.io/g/devel/message/39968 > Mute This Topic: https://groups.io/mt/31489698/1761188 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [ard.biesheuvel@linaro.org] > ------------ >