From: "Ard Biesheuvel" <ard.biesheuvel@linaro.org>
To: edk2-devel-groups-io <devel@edk2.groups.io>,
Marcin Wojtas <mw@semihalf.com>
Cc: "Leif Lindholm" <leif.lindholm@linaro.org>,
"Jan Dąbroś" <jsd@semihalf.com>,
"Grzegorz Jaszczyk" <jaz@semihalf.com>,
"Kostya Porotchkin" <kostap@marvell.com>,
"Jici Gao" <Jici.Gao@arm.com>,
"Rebecca Cran" <rebecca@bluestop.org>,
"Mark Kettenis" <kettenis@jive.eu>
Subject: Re: [edk2-devel] [edk2-platforms: PATCH 11/14] Marvell/Armada70x0Db: Enable ACPI PCIE support
Date: Thu, 16 May 2019 16:26:14 +0200 [thread overview]
Message-ID: <CAKv+Gu8g3UJPAgVjzxq-6Mqx93GvX=xaR+dbFd3Aiw1m9aMR-Q@mail.gmail.com> (raw)
In-Reply-To: <1557395622-32425-12-git-send-email-mw@semihalf.com>
On Thu, 9 May 2019 at 11:54, Marcin Wojtas <mw@semihalf.com> wrote:
>
> This patch adds description of the PCIE controller in
> ACPI tables of Armada 7040 DB board.
>
Idem
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf | 1 +
> Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h | 25 +++
> Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 217 ++++++++++++++++++++
> Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc | 47 +++++
> 4 files changed, 290 insertions(+)
> create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h
> create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc
>
> diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf
> index 659c333..96bcdf0 100644
> --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf
> +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf
> @@ -25,6 +25,7 @@
>
> [Sources]
> Armada70x0Db/Dsdt.asl
> + Armada70x0Db/Mcfg.aslc
> Fadt.aslc
> Gtdt.aslc
> Madt.aslc
> diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h
> new file mode 100644
> index 0000000..93631c2
> --- /dev/null
> +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h
> @@ -0,0 +1,25 @@
> +/**
> +
> + Copyright (C) 2019, Marvell International Ltd. and its affiliates.
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#define PCI_BUS_MIN 0x0
> +#define PCI_BUS_MAX 0x0
> +#define PCI_BUS_COUNT 0x1
> +#define PCI_MMIO32_BASE 0xC0000000
> +#define PCI_MMIO32_SIZE 0x20000000
> +#define PCI_MMIO64_BASE 0x800000000
> +#define PCI_MMIO64_SIZE 0x100000000
> +#define PCI_IO_BASE 0x0
> +#define PCI_IO_SIZE 0x10000
> +#define PCI_IO_TRANSLATION 0xEFF00000
> +#define PCI_ECAM_BASE 0xE0008000
> diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
> index 621b688..a23bd70 100644
> --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
> +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
> @@ -15,6 +15,7 @@
>
> **/
>
> +#include "Armada70x0Db/Pcie.h"
> #include "IcuInterrupts.h"
>
> DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
> @@ -225,5 +226,221 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
> }
> })
> }
> +
> + //
> + // PCIe Root Bus
> + //
> + Device (PCI0)
> + {
> + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
> + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
> + Name (_SEG, 0x00) // _SEG: PCI Segment
> + Name (_BBN, 0x00) // _BBN: BIOS Bus Number
> + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
> + Name (_PRT, Package () // _PRT: PCI Routing Table
> + {
> + Package () { 0xFFFF, 0x0, 0x0, 0x40 },
> + Package () { 0xFFFF, 0x1, 0x0, 0x40 },
> + Package () { 0xFFFF, 0x2, 0x0, 0x40 },
> + Package () { 0xFFFF, 0x3, 0x0, 0x40 }
> + })
> +
> + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
> + {
> + Name (RBUF, ResourceTemplate ()
> + {
> + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
> + 0x0000, // Granularity
> + PCI_BUS_MIN, // Range Minimum
> + PCI_BUS_MAX, // Range Maximum
> + 0x0000, // Translation Offset
> + PCI_BUS_COUNT // Length
> + )
> + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
> + 0x00000000, // Granularity
> + PCI_MMIO32_BASE, // Range Minimum
> + 0xDFFFFFFF, // Range Maximum
> + 0x00000000, // Translation Offset
> + PCI_MMIO32_SIZE // Length
> + )
> + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
> + 0x0000000000000000, // Granularity
> + PCI_MMIO64_BASE, // Range Minimum
> + 0x8FFFFFFFF, // Range Maximum
> + 0x00000000, // Translation Offset
> + PCI_MMIO64_SIZE // Length
> + )
> + DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
> + 0x00000000, // Granularity
> + PCI_IO_BASE, // Range Minimum
> + 0x0000FFFF, // Range Maximum
> + PCI_IO_TRANSLATION, // Translation Address
> + PCI_IO_SIZE, // Length
> + ,
> + ,
> + ,
> + TypeTranslation
> + )
> + })
> + Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */
> + } // Method(_CRS)
> +
> + Device (RES0)
> + {
> + Name (_HID, "PNP0C02")
> + Name (_CRS, ResourceTemplate ()
> + {
> + Memory32Fixed (ReadWrite,
> + PCI_ECAM_BASE,
> + 0x10000000
> + )
> + })
> + }
> + Name (SUPP, 0x00)
> + Name (CTRL, 0x00)
> + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
> + {
> + CreateDWordField (Arg3, 0x00, CDW1)
> + If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
> + {
> + CreateDWordField (Arg3, 0x04, CDW2)
> + CreateDWordField (Arg3, 0x08, CDW3)
> + Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */
> + Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */
> + If (LNotEqual (And (SUPP, 0x16), 0x16))
> + {
> + And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */
> + }
> +
> + And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */
> + If (LNotEqual (Arg1, One))
> + {
> + Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
> + }
> +
> + If (LNotEqual (CDW3, CTRL))
> + {
> + Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
> + }
> +
> + Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */
> + Return (Arg3)
> + }
> + Else
> + {
> + Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
> + Return (Arg3)
> + }
> + } // Method(_OSC)
> +
> + //
> + // Device-Specific Methods
> + //
> + Method(_DSM, 0x4, NotSerialized) {
> + If (LEqual(Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
> + switch (ToInteger(Arg2)) {
> + //
> + // Function 0: Return supported functions
> + //
> + case(0) {
> + Return (Buffer() {0xFF})
> + }
> +
> + //
> + // Function 1: Return PCIe Slot Information
> + //
> + case(1) {
> + Return (Package(2) {
> + One, // Success
> + Package(3) {
> + 0x1, // x1 PCIe link
> + 0x1, // PCI express card slot
> + 0x1 // WAKE# signal supported
> + }
> + })
> + }
> +
> + //
> + // Function 2: Return PCIe Slot Number.
> + //
> + case(2) {
> + Return (Package(1) {
> + Package(4) {
> + 2, // Source ID
> + 4, // Token ID: ID refers to a slot
> + 0, // Start bit of the field to use.
> + 7 // End bit of the field to use.
> + }
> + })
> + }
> +
> + //
> + // Function 4: Return PCI Bus Capabilities
> + //
> + case(4) {
> + Return (Package(2) {
> + One, // Success
> + Buffer() {
> + 1,0, // Version
> + 0,0, // Status, 0:Success
> + 24,0,0,0, // Length
> + 1,0, // PCI
> + 16,0, // Length
> + 0, // Attributes
> + 0x0D, // Current Speed/Mode
> + 0x3F,0, // Supported Speeds/Modes
> + 0, // Voltage
> + 0,0,0,0,0,0,0 // Reserved
> + }
> + })
> + }
> +
> + //
> + // Function 5: Return Ignore PCI Boot Configuration
> + //
> + case(5) {
> + Return (Package(1) {1})
> + }
> +
> + //
> + // Function 6: Return LTR Maximum Latency
> + //
> + case(6) {
> + Return (Package(4) {
> + Package(1){0}, // Maximum Snoop Latency Scale
> + Package(1){0}, // Maximum Snoop Latency Value
> + Package(1){0}, // Maximum No-Snoop Latency Scale
> + Package(1){0} // Maximum No-Snoop Latency Value
> + })
> + }
> +
> + //
> + // Function 7: Return PCI Express Naming
> + //
> + case(7) {
> + Return (Package(2) {
> + Package(1) {0},
> + Package(1) {Unicode("PCI0")}
> + })
> + }
> +
> + //
> + // Not supported
> + //
> + default {
> + }
> + }
> + }
> + Return (Buffer(){0})
> + } // Method(_DSM)
> +
> + //
> + // Root-Complex 0
> + //
> + Device (RP0)
> + {
> + Name (_ADR, PCI_ECAM_BASE) // _ADR: Bus 0, Dev 0, Func 0
> + }
> + }
> }
> }
> diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc
> new file mode 100644
> index 0000000..90bf163
> --- /dev/null
> +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc
> @@ -0,0 +1,47 @@
> +/** @file
> +
> + Memory mapped config space base address table (MCFG)
> +
> + Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> + Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/AcpiLib.h>
> +
> +#include "AcpiHeader.h"
> +#include "Armada70x0Db/Pcie.h"
> +
> +#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
> +
> +#pragma pack(1)
> +typedef struct {
> + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
> + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure;
> +} ACPI_6_0_MCFG_STRUCTURE;
> +#pragma pack()
> +
> +STATIC ACPI_6_0_MCFG_STRUCTURE Mcfg = {
> + {
> + __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
> + ACPI_6_0_MCFG_STRUCTURE,
> + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
> + EFI_ACPI_RESERVED_QWORD
> + }, {
> + PCI_ECAM_BASE, // BaseAddress
> + 0, // PciSegmentGroupNumber
> + PCI_BUS_MIN, // StartBusNumber
> + PCI_BUS_MAX, // EndBusNumber
> + EFI_ACPI_RESERVED_DWORD // Reserved
> + }
> +};
> +
> +VOID CONST * CONST ReferenceAcpiTable = &Mcfg;
> --
> 2.7.4
>
>
>
>
next prev parent reply other threads:[~2019-05-16 14:26 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-09 9:53 [edk2-platforms: PATCH 00/14] Armada7k8k PCIE support Marcin Wojtas
2019-05-09 9:53 ` [edk2-platforms: PATCH 01/14] Marvell/Library: MvGpioLib: Extend GPIO pin description Marcin Wojtas
2019-05-09 9:53 ` [edk2-platforms: PATCH 02/14] Marvell/Library: ArmadaSoCDescLib: Add PCIE information Marcin Wojtas
2019-05-10 14:59 ` Leif Lindholm
2019-05-10 15:03 ` Marcin Wojtas
2019-05-09 9:53 ` [edk2-platforms: PATCH 03/14] Marvell/Library: ArmadaBoardDescLib: " Marcin Wojtas
2019-05-16 13:57 ` Ard Biesheuvel
2019-05-09 9:53 ` [edk2-platforms: PATCH 04/14] Marvell/Armada7k8k: Extend board description libraries with PCIE Marcin Wojtas
2019-05-09 10:16 ` Marcin Wojtas
2019-05-09 9:53 ` [edk2-platforms: PATCH 05/14] Marvell/Armada7k8k: MvBoardDesc: Extend protocol with PCIE support Marcin Wojtas
2019-05-16 13:53 ` Ard Biesheuvel
2019-05-09 9:53 ` [edk2-platforms: PATCH 06/14] Marvell/Armada7k8k: Add PciExpressLib implementation Marcin Wojtas
2019-05-10 15:25 ` Leif Lindholm
2019-05-10 15:29 ` Marcin Wojtas
2019-05-16 14:02 ` Ard Biesheuvel
2019-05-16 14:26 ` Marcin Wojtas
2019-05-09 9:53 ` [edk2-platforms: PATCH 07/14] Marvell/Armada7k8k: Implement PciHostBridgeLib Marcin Wojtas
2019-05-10 15:50 ` Leif Lindholm
2019-05-12 11:41 ` Marcin Wojtas
2019-05-16 14:14 ` Ard Biesheuvel
2019-05-09 9:53 ` [edk2-platforms: PATCH 08/14] Marvell/Armada7k8k: Enable PCIE support Marcin Wojtas
2019-05-16 14:16 ` Ard Biesheuvel
2019-05-16 14:22 ` Marcin Wojtas
2019-05-16 14:25 ` Ard Biesheuvel
2019-05-16 14:32 ` Leif Lindholm
2019-05-09 9:53 ` [edk2-platforms: PATCH 09/14] Marvell/Armada80x0McBin: Enable ACPI " Marcin Wojtas
2019-05-10 15:54 ` Leif Lindholm
2019-05-16 14:23 ` Ard Biesheuvel
2019-05-09 9:53 ` [edk2-platforms: PATCH 10/14] Marvell/Armada80x0Db: " Marcin Wojtas
2019-05-16 14:25 ` [edk2-devel] " Ard Biesheuvel
2019-05-09 9:53 ` [edk2-platforms: PATCH 11/14] Marvell/Armada70x0Db: " Marcin Wojtas
2019-05-16 14:26 ` Ard Biesheuvel [this message]
2019-05-09 9:53 ` [edk2-platforms: PATCH 12/14] Marvell/Armada80x0McBin: DeviceTree: Use pci-host-generic driver Marcin Wojtas
2019-05-09 9:53 ` [edk2-platforms: PATCH 13/14] Marvell/Armada7k8k: Remove duplication in .dsc files Marcin Wojtas
2019-05-09 9:53 ` [edk2-platforms: PATCH 14/14] Marvell/Armada7k8: Add 'acpiview' shell command to build Marcin Wojtas
2019-05-10 15:58 ` [edk2-platforms: PATCH 00/14] Armada7k8k PCIE support Leif Lindholm
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