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From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>,
	Leif Lindholm <leif.lindholm@linaro.org>
Cc: Heyi Guo <heyi.guo@linaro.org>,
	Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: Re: [PATCH 2/4] ArmPkg/ArmLib: AARCH64: set frame pointer in cache maintenance routine
Date: Wed, 22 Feb 2017 12:56:04 +0000	[thread overview]
Message-ID: <CAKv+Gu8gQYY7mB0TjDbXafPvU4VtSKcrUeSS3kLXa0VOtx0nuA@mail.gmail.com> (raw)
In-Reply-To: <1487756301-15646-3-git-send-email-ard.biesheuvel@linaro.org>

On 22 February 2017 at 09:38, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> Stack and unstack the frame pointer according to the AAPCS in
> AArch64AllDataCachesOperation ().
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
> index 5cee7c1519c3..c35c05fdf681 100644
> --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
> +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
> @@ -273,7 +273,7 @@ ASM_FUNC(ArmDisableBranchPrediction)
>  ASM_FUNC(AArch64AllDataCachesOperation)
>  // We can use regs 0-7 and 9-15 without having to save/restore.
>  // Save our link register on the stack. - The stack must always be quad-word aligned
> -  str   x30, [sp, #-16]!
> +  stp   x29, x30, [sp, #-16]!

As discussed over IRC, this needs

mov x29, sp

appended as well.

This ensures that this function will show up in a backtrace when an
exception is taken (and not handled) in the callback invoked by this
function. Without setting (and preserving) x29, it will still point to
the caller of AArch64AllDataCachesOperation()

>    mov   x1, x0                  // Save Function call in x1
>    mrs   x6, clidr_el1           // Read EL1 CLIDR
>    and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)
> @@ -324,7 +324,7 @@ L_Skip:
>  L_Finished:
>    dsb   sy
>    isb
> -  ldr   x30, [sp], #0x10
> +  ldp   x29, x30, [sp], #0x10
>    ret
>
>
> --
> 2.7.4
>


  reply	other threads:[~2017-02-22 12:56 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-22  9:38 [PATCH 0/4] AARCH64: enable stack alignment check Ard Biesheuvel
2017-02-22  9:38 ` [PATCH 1/4] ArmPlatformPkg/ArmPlatformStackLib: use callee preserved registers Ard Biesheuvel
2017-02-22 12:06   ` Leif Lindholm
2017-02-22 12:52     ` Ard Biesheuvel
2017-02-22 13:11       ` Leif Lindholm
2017-02-22  9:38 ` [PATCH 2/4] ArmPkg/ArmLib: AARCH64: set frame pointer in cache maintenance routine Ard Biesheuvel
2017-02-22 12:56   ` Ard Biesheuvel [this message]
2017-02-22 13:12     ` Leif Lindholm
2017-02-22  9:38 ` [PATCH 3/4] ArmPkg/ArmLib: AARCH64: allow the stack aligment (SA) bit to be managed Ard Biesheuvel
2017-02-22 12:13   ` Leif Lindholm
2017-02-22  9:38 ` [PATCH 4/4] ArmPkg/ArmMmuLib: AARCH64: enable stack alignment checking Ard Biesheuvel
2017-02-22 12:14   ` Leif Lindholm
2017-02-22 13:23 ` [PATCH 0/4] AARCH64: enable stack alignment check Ard Biesheuvel

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