From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-it0-x231.google.com (mail-it0-x231.google.com [IPv6:2607:f8b0:4001:c0b::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C8004203BF024 for ; Wed, 5 Apr 2017 14:55:50 -0700 (PDT) Received: by mail-it0-x231.google.com with SMTP id a140so16791863ita.0 for ; Wed, 05 Apr 2017 14:55:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=TN3275diQkJ77wILTBgQdwmfH/ejjsREXByIhZrlxDY=; b=Wi4hGpMAE5SGtR0+Og6vnOV2RDoaibu+7Zaclj/SfLlH/WdzVTS5YmUkfh4oP9+gG2 LYEzlmnMsbe9L9/5nJhhiOhzNp/9LnzmIJ6bdIU8kFjfIOA7hsyjg8tOmtDPzRtWLqrX VxFCONoagkIHYolNGjN8tWe2cd0jyigU374hk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=TN3275diQkJ77wILTBgQdwmfH/ejjsREXByIhZrlxDY=; b=WVv6urMkf2yuAjNNzc1mLmHjQulth9pZ2OcbxCCNB4SJYBp6iioohNtNsFf3bsbeTn q+b12NUn4HZSgf/mMD+qQaV70qBHkvJPiN+X+3/xeG+cmjjzwUtSN5T4AuODho0bsznD yJpmTX0lgKIaFjWezP8GBeLgQIGZfILlkJs/TQpup3Cui9lm3sTvqihNrre/iDF9bIRK Y0XyAaj6PHWD+lZT89Mc0/6Wncor67CsTpOgVpNAGkoXR5oraBWe2VMXt6jpJoAzVGJq 6gq8o75xAnqabdsKeneggbsnAUBOaTQ+rf9YkYnTymoVp61SATQ2xQgSZ81Ast+G0rnj baPg== X-Gm-Message-State: AFeK/H1E6Dew5h9nZFTcsmVWWzVADBX8+QOGny1ge16HOIXgsuK/Iiuzo0OjX1y+TYeWVIV4qx6WTqMY4G2x6lOP X-Received: by 10.36.46.69 with SMTP id i66mr22673050ita.59.1491429350067; Wed, 05 Apr 2017 14:55:50 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.10.27 with HTTP; Wed, 5 Apr 2017 14:55:49 -0700 (PDT) In-Reply-To: <8871a794-80f8-049f-5abc-ca1d4a8fb3a3@arm.com> References: <1473429644-13480-1-git-send-email-ard.biesheuvel@linaro.org> <1473429644-13480-5-git-send-email-ard.biesheuvel@linaro.org> <8871a794-80f8-049f-5abc-ca1d4a8fb3a3@arm.com> From: Ard Biesheuvel Date: Wed, 5 Apr 2017 22:55:49 +0100 Message-ID: To: Jeremy Linton Cc: Leif Lindholm , "edk2-devel@lists.01.org" , "Gao, Liming" , "Kinney, Michael D" Subject: Re: [PATCH v5 4/4] MdePkg/BaseMemoryLibOptDxe ARM|AARCH64: disallow use in SEC & PEI phases X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 Apr 2017 21:55:51 -0000 Content-Type: text/plain; charset=UTF-8 On 5 April 2017 at 22:28, Jeremy Linton wrote: > Hi, > > > On 04/05/2017 03:34 PM, Ard Biesheuvel wrote: >> >> On 5 April 2017 at 21:12, Jeremy Linton wrote: >>> >>> Hi, >>> >>> On 09/09/2016 09:00 AM, Ard Biesheuvel wrote: >>>> >>>> >>>> The new accelerated ARM and AARCH64 implementations take advantage of >>>> features that are only available when the MMU and Dcache are on. So >>>> restrict the use of this library to the DXE phase or later. >>> >>> >>> >>> I don't think this is sufficient because DC ZVA doesn't work against >>> device >>> memory/etc. That means that users have to somehow know the page/etc >>> attributes of memory regions before they call SetMemXX() on them. >>> >> >> Yes. I literally found this out myself yesterday. Note that this >> applies equally to unaligned accesses. >> >> >>> I think this is a problem because nowhere in the UEFI specs do I see such >>> restrictions on those memory operations. >>> >> >> Using device attributes for memory is something we should ban for >> AArch64 in the spec. >> >>> For a specific problematic example, the LcdGraphicsOutputBlt.c uses it >>> for >>> BltVideoFill() and the target of that is likely not regular cached video >>> memory. >>> >> >> Those drivers should be using EFI_MEMORY_WC not EFI_MEMORY_UC for the >> VRAM mapping. Note that EFI_MEMORY_UC is nGnRnE which is unnecessarily >> restrictive. >> >> I agree there is a general issue here which we should address by >> tightening the spec. I don't see a lot of value in avoiding DC ZVA and >> unaligned accesses altogether, I'd rather fix the code instead. > > > > While I agree with the general sentiment, I find the result brittle. If it > were used as a DEBUG build way to locate sub-optmimal code I would be more > on board. But shipping it like this, puts it into situations where the user > inadvertently changes something (say making the background black and > therefore triggering the DC) or some obscure option ROM (we will get there > right??!!) triggers it in a place where it can't be debugged. > > Particularly since we are talking boot, where the few percent perf > improvement on this operation is likely completely undetectable. The one > place where I can think it might even be measurable is in routines to clear > system memory, and those routines could be a special case anyway. > I guess this depends on the use case. For server, it may not matter, but the case is different for mobile, and the Broadcom engineers that did some benchmarks on this code were very pleased with the result (and the speedup was significant, although I don't know which routines are the hotspots) As for option ROMs: those will link to their own BaseMemoryLib implementation (assuming that they are EDK2 based) so the only way they would have access to these routines is via the CopyMem() and SetMem() boot services. Note that that does not dismiss the concern at all, it is just a clarification. Leif, any thoughts?