From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: Marcin Wojtas <mw@semihalf.com>
Cc: "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>,
"Leif Lindholm" <leif.lindholm@linaro.org>,
"Nadav Haklai" <nadavh@marvell.com>,
"Neta Zur Hershkovits" <neta@marvell.com>,
"Kostya Porotchkin" <kostap@marvell.com>,
jinghua@marvell.com, "Alexander Graf" <agraf@suse.de>,
"Jan Dąbroś" <jsd@semihalf.com>
Subject: Re: [platforms: PATCH 1/7] Drivers/Net/Pp2Dxe: Move registers' description to macros
Date: Fri, 1 Sep 2017 10:22:41 +0100 [thread overview]
Message-ID: <CAKv+Gu8n1tWUpgfQD8kACfj-LTvrRD1xtGnb16Gi9bsXSu6LRQ@mail.gmail.com> (raw)
In-Reply-To: <1504233451-6455-2-git-send-email-mw@semihalf.com>
On 1 September 2017 at 03:37, Marcin Wojtas <mw@semihalf.com> wrote:
> Registers' offset are constant for each PP2 controller instance,
> so use macros with relative addresses for their description.
> This allowed to remove 5 PCD's and will ease enabling second
> controller on Armada8k. Update PortingGuide accordingly.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> Platform/Marvell/Armada/Armada70x0.dsc | 6 ------
> Platform/Marvell/Documentation/PortingGuide/Pp2.txt | 21 ---------------------
> Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h | 10 ++++++++++
> Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 12 ++++++------
> Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 6 ------
> Platform/Marvell/Marvell.dec | 6 ------
> 6 files changed, 16 insertions(+), 45 deletions(-)
>
> diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Armada/Armada70x0.dsc
> index ccfd43c..d77e0b6 100644
> --- a/Platform/Marvell/Armada/Armada70x0.dsc
> +++ b/Platform/Marvell/Armada/Armada70x0.dsc
> @@ -122,18 +122,12 @@
> #NET
> gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 }
> gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|333333333
> - gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress|0xf2130e00
> - gMarvellTokenSpaceGuid.PcdPp2GmacDevSize|0x1000
> gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
> gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x1, 0x1, 0x0 }
> gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x3, 0x4, 0x3 }
> gMarvellTokenSpaceGuid.PcdPp2NumPorts|3
> gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
> - gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress|0xf2441000
> gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0xf2000000
> - gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress|0xf212A200
> - gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress|0xf2130f00
> - gMarvellTokenSpaceGuid.PcdPp2XlgDevSize|0x1000
>
> #PciEmulation
> gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 }
> diff --git a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
> index c1554a6..3c2f418 100644
> --- a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
> +++ b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
> @@ -34,26 +34,5 @@ PHY_SPEED (in Mbps) is defined as follows:
> Base address of shared register space of PP2:
> gMarvellTokenSpaceGuid.PcdPp2SharedAddress
>
> -Spacing between consecutive GMAC register spaces:
> - gMarvellTokenSpaceGuid.PcdPp2GmacDevSize
> -
> -Base address of GMAC:
> - gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress
> -
> -Spacing between consecutive XLG register spaces:
> - gMarvellTokenSpaceGuid.PcdPp2XlgDevSize
> -
> -Base address of XLG:
> - gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress
> -
> -Base address of RFU1:
> - gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress
> -
> -Base address of SMI:
> - gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress
> -
> TCLK frequency in Hz:
> gMarvellTokenSpaceGuid.PcdPp2ClockFrequency
> -
> -GMAC and XLG addresses are computed as follows:
> - address = base_address + dev_size * gop_index
> diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
> index f283db2..868be53 100644
> --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
> +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
> @@ -39,6 +39,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> #define BIT(nr) (1 << (nr))
> #endif
>
> +/* PP2v2 registers offsets */
> +#define MVPP22_SMI_OFFSET 0x12a200
> +#define MVPP22_MPCS_OFFSET 0x130000
> +#define MVPP22_XPCS_OFFSET 0x130400
> +#define MVPP22_GMAC_OFFSET 0x130e00
> +#define MVPP22_GMAC_REG_SIZE 0x1000
> +#define MVPP22_XLG_OFFSET 0x130f00
> +#define MVPP22_XLG_REG_SIZE 0x1000
> +#define MVPP22_RFU1_OFFSET 0x441000
> +
> /* RX Fifo Registers */
> #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
> #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
> diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
> index 1e2ccd0..d53f3b7 100644
> --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
> +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
> @@ -1141,10 +1141,6 @@ Pp2DxeParsePortPcd (
> Pp2Context->Port.PhyInterface = PhyConnectionTypes[Pp2Context->Instance];
> Pp2Context->Port.AlwaysUp = AlwaysUp[Pp2Context->Instance];
> Pp2Context->Port.Speed = Speed[Pp2Context->Instance];
> - Pp2Context->Port.GmacBase = PcdGet64 (PcdPp2GmacBaseAddress) +
> - PcdGet32 (PcdPp2GmacDevSize) * Pp2Context->Port.GopIndex;
> - Pp2Context->Port.XlgBase = PcdGet64 (PcdPp2XlgBaseAddress) +
> - PcdGet32 (PcdPp2XlgDevSize) * Pp2Context->Port.GopIndex;
> }
>
> EFI_STATUS
> @@ -1174,8 +1170,8 @@ Pp2DxeInitialise (
> }
>
> Mvpp2Shared->Base = PcdGet64 (PcdPp2SharedAddress);
> - Mvpp2Shared->Rfu1Base = PcdGet64 (PcdPp2Rfu1BaseAddress);
> - Mvpp2Shared->SmiBase = PcdGet64 (PcdPp2SmiBaseAddress);
> + Mvpp2Shared->Rfu1Base = Mvpp2Shared->Base + MVPP22_RFU1_OFFSET;
> + Mvpp2Shared->SmiBase = Mvpp2Shared->Base + MVPP22_SMI_OFFSET;
> Mvpp2Shared->Tclk = PcdGet32 (PcdPp2ClockFrequency);
>
> /* Prepare buffers */
> @@ -1259,6 +1255,10 @@ Pp2DxeInitialise (
> Pp2Context->Port.TxpNum = 1;
> Pp2Context->Port.Priv = Mvpp2Shared;
> Pp2Context->Port.FirstRxq = 4 * Pp2Context->Instance;
> + Pp2Context->Port.GmacBase = Mvpp2Shared->Base + MVPP22_GMAC_OFFSET +
> + MVPP22_GMAC_REG_SIZE * Pp2Context->Port.GopIndex;
> + Pp2Context->Port.XlgBase = Mvpp2Shared->Base + MVPP22_XLG_OFFSET +
> + MVPP22_XLG_REG_SIZE * Pp2Context->Port.GopIndex;
>
> /* Gather accumulated configuration data of all ports' MAC's */
> NetCompConfig |= MvpPp2xGop110NetcCfgCreate(&Pp2Context->Port);
> diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
> index 9052fe2..ecd82b6 100644
> --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
> +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
> @@ -74,18 +74,12 @@
> gMarvellTokenSpaceGuid.PcdPhyConnectionTypes
> gMarvellTokenSpaceGuid.PcdPhySmiAddresses
> gMarvellTokenSpaceGuid.PcdPp2ClockFrequency
> - gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress
> - gMarvellTokenSpaceGuid.PcdPp2GmacDevSize
> gMarvellTokenSpaceGuid.PcdPp2GopIndexes
> gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
> gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
> gMarvellTokenSpaceGuid.PcdPp2NumPorts
> gMarvellTokenSpaceGuid.PcdPp2PortIds
> - gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress
> gMarvellTokenSpaceGuid.PcdPp2SharedAddress
> - gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress
> - gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress
> - gMarvellTokenSpaceGuid.PcdPp2XlgDevSize
>
> [Depex]
> TRUE
> diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec
> index 5cbf0c3..9e2f706 100644
> --- a/Platform/Marvell/Marvell.dec
> +++ b/Platform/Marvell/Marvell.dec
> @@ -170,18 +170,12 @@
> #NET
> gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024
> gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|0|UINT32|0x3000026
> - gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress|0|UINT64|0x3000027
> - gMarvellTokenSpaceGuid.PcdPp2GmacDevSize|0|UINT32|0x3000028
> gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029
> gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A
> gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B
> gMarvellTokenSpaceGuid.PcdPp2NumPorts|0|UINT32|0x300002D
> gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C
> - gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress|0|UINT64|0x300002E
> gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0|UINT64|0x300002F
> - gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress|0|UINT64|0x3000030
> - gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress|0|UINT64|0x3000031
> - gMarvellTokenSpaceGuid.PcdPp2XlgDevSize|0|UINT32|0x3000032
>
> #PciEmulation
> gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 }|VOID*|0x3000033
> --
> 1.8.3.1
>
next prev parent reply other threads:[~2017-09-01 9:19 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-01 2:37 [platforms: PATCH 0/7] Armada 70x0/80x0 network improvements Marcin Wojtas
2017-09-01 2:37 ` [platforms: PATCH 1/7] Drivers/Net/Pp2Dxe: Move registers' description to macros Marcin Wojtas
2017-09-01 9:22 ` Ard Biesheuvel [this message]
2017-09-01 2:37 ` [platforms: PATCH 2/7] Drivers/Net/Pp2Dxe: Add SFI support Marcin Wojtas
2017-09-01 9:26 ` Ard Biesheuvel
2017-09-01 9:39 ` Marcin Wojtas
2017-09-01 9:40 ` Ard Biesheuvel
2017-09-01 9:49 ` Marcin Wojtas
2017-09-01 9:51 ` Ard Biesheuvel
2017-09-01 2:37 ` [platforms: PATCH 3/7] Drivers/Net/Pp2Dxe: Support multiple ethernet ports simultaneously Marcin Wojtas
2017-09-01 9:30 ` Ard Biesheuvel
2017-09-01 2:37 ` [platforms: PATCH 4/7] Drivers/Net/Pp2Dxe: Increase amount of ingress resources Marcin Wojtas
2017-09-01 9:30 ` Ard Biesheuvel
2017-09-01 2:37 ` [platforms: PATCH 5/7] Platforms/Marvell: Update ethernet ports types on A70x0 DB Marcin Wojtas
2017-09-01 9:31 ` Ard Biesheuvel
2017-09-01 2:37 ` [platforms: PATCH 6/7] Drivers/Net/Pp2Dxe: Move devices description to MvHwDescLib Marcin Wojtas
2017-09-01 9:33 ` Ard Biesheuvel
2017-09-01 2:37 ` [platforms: PATCH 7/7] Drivers/Net/Pp2Dxe: Enable using ports from different controllers Marcin Wojtas
2017-09-01 9:34 ` Ard Biesheuvel
2017-09-01 9:27 ` [platforms: PATCH 0/7] Armada 70x0/80x0 network improvements Ard Biesheuvel
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