From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: Leif Lindholm <leif.lindholm@linaro.org>
Cc: "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>,
Joakim Bech <joakim.bech@linaro.org>
Subject: Re: [PATCH edk2-platforms 1/5] Silicon/SynQuaver/DeviceTree: add node for SPI controller
Date: Fri, 16 Feb 2018 18:34:30 +0000 [thread overview]
Message-ID: <CAKv+Gu8qEBiVn1jwd7=97Yy9gf2TMSCQT_bonieuYbLCmJndGQ@mail.gmail.com> (raw)
In-Reply-To: <20180216170020.inkadbvnr25zczhh@bivouac.eciton.net>
On 16 February 2018 at 17:00, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Thu, Feb 15, 2018 at 05:20:50PM +0000, Ard Biesheuvel wrote:
>> Add a node for the SPI controller to the device tree so the OS may
>> attach to it. This is the SPI controller that is attached to the
>> 96boards mezzanine connector on Developer Box.
>
> Just a generic question (which also applies to the subsequent patch):
> Are there any implications here with regards to this bus running in
> master or slave mode?
>
Not really, since that depends entirely on the OS. We just assert the
presence of a certain IP block at a certain memory offset, and whether
the hardware supports slave mode is left unspecified. Whether the OS
supports slave mode (for this particular IP block) is not a property
of the hardware.
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> ---
>> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
>> index 9085adb326ab..ba445a50f16f 100644
>> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
>> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
>> @@ -538,4 +538,22 @@
>> clock-names = "core", "iface";
>> dma-coherent;
>> };
>> +
>> + clk_alw_1_8: spi_ihclk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <125000000>;
>> + clock-output-names = "iHCLK";
>> + };
>> +
>> + spi: spi@54810000 {
>> + compatible = "socionext,synquacer-spi";
>> + reg = <0x0 0x54810000 0x0 0x1000>;
>> + clocks = <&clk_alw_1_8>;
>> + clock-names = "iHCLK";
>> + socionext,use-rtm;
>> + socionext,set-aces;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> };
>> --
>> 2.11.0
>>
next prev parent reply other threads:[~2018-02-16 18:28 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-15 17:20 [PATCH edk2-platforms 0/5] Add Secure96 mezzanine support Ard Biesheuvel
2018-02-15 17:20 ` [PATCH edk2-platforms 1/5] Silicon/SynQuaver/DeviceTree: add node for SPI controller Ard Biesheuvel
2018-02-16 17:00 ` Leif Lindholm
2018-02-16 18:34 ` Ard Biesheuvel [this message]
2018-02-18 11:39 ` Leif Lindholm
2018-02-19 8:20 ` Ard Biesheuvel
2018-02-19 11:48 ` Leif Lindholm
2018-02-15 17:20 ` [PATCH edk2-platforms 2/5] Silicon/SynQuaver/DeviceTree: add node for I2C controller Ard Biesheuvel
2018-02-15 17:20 ` [PATCH edk2-platforms 3/5] Platform: add support for 96boards Secure96 mezzanine adapter Ard Biesheuvel
2018-02-15 17:20 ` [PATCH edk2-platforms 4/5] Silicon/SynQuacer/PlatformDxe: add menu option to select mezzanine Ard Biesheuvel
2018-02-15 17:20 ` [PATCH edk2-platforms 5/5] Platform/Socionext/DeveloperBox: add Secure96 support Ard Biesheuvel
2018-02-16 17:35 ` [PATCH edk2-platforms 0/5] Add Secure96 mezzanine support Leif Lindholm
2018-02-16 18:41 ` Ard Biesheuvel
2018-02-21 12:10 ` Ard Biesheuvel
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