From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::244; helo=mail-it0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x244.google.com (mail-it0-x244.google.com [IPv6:2607:f8b0:4001:c0b::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DE400223230F7 for ; Fri, 16 Feb 2018 10:28:37 -0800 (PST) Received: by mail-it0-x244.google.com with SMTP id j21so4520754ita.1 for ; Fri, 16 Feb 2018 10:34:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=RKPApmW4WF/Pt3eNUPmLwWBv0L1G7GjpdTy4CadsOAs=; b=YjP8fTaedL+TeOx/LGIWg1FC1qba699MP4nRaL5IuSwEXYd/IStlAuRgNSQH23UzEX Qu4VKsDLj90XH5VVhOYeoCyhaPmDa5/fgUqNnZN9iHRVreEyDM+2qjUo+zlGyB6Ucp/W 1lLNC0S8ygeeJmfl/dboEddmq5EoYYaWvJuvo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=RKPApmW4WF/Pt3eNUPmLwWBv0L1G7GjpdTy4CadsOAs=; b=iqRw4e1zfyqMbKQuCIu81eXP0ghZnUMmnImZdxs9yMG1RQVuw+leeNYENCwskAlvet XHuIE44o3YqX49ywnEtYV5xHt/m94ZDAoDrjWSWTZfnn3dJGe1JXIcY5qxiQsdSq2K0v tZANOWtsi8ts9tq5CeWIXwXIrbH3j1klNR7GdaYudTAagfaiKeVA64lsHvlcdReR8FsN peSkm4ufjEyhLHb2FiQ3CK0YD/qYUlVLA0eQsWo6wCNCdSBiPocDKStNvGGfUV3+v7gH VE0L5bezcXMJ8DLjAY3vYkKoqmAzw3++4vlvVFNliwkAg2ji16Syr9HxsXIbq96hTxjp 77vw== X-Gm-Message-State: APf1xPDksfqpeLwvv4NuTVkkcWoFrCaOTWSCQrK0rr1/mdxL3YJy9DMq wiwyJ5chT8eptNJq48MgsXmcPrvwAysJcIR0Ndaqmg== X-Google-Smtp-Source: AH8x227nrxTZ6TwNPA+e6A7+3THllmHm5QvhcdcAm749KL/AatKijX2LPqBgSkx5qqX+DkNQVR7JiAQGueQIHGhk2oQ= X-Received: by 10.36.172.10 with SMTP id s10mr9285823ite.42.1518806070918; Fri, 16 Feb 2018 10:34:30 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.138.209 with HTTP; Fri, 16 Feb 2018 10:34:30 -0800 (PST) In-Reply-To: <20180216170020.inkadbvnr25zczhh@bivouac.eciton.net> References: <20180215172054.27452-1-ard.biesheuvel@linaro.org> <20180215172054.27452-2-ard.biesheuvel@linaro.org> <20180216170020.inkadbvnr25zczhh@bivouac.eciton.net> From: Ard Biesheuvel Date: Fri, 16 Feb 2018 18:34:30 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Joakim Bech Subject: Re: [PATCH edk2-platforms 1/5] Silicon/SynQuaver/DeviceTree: add node for SPI controller X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Feb 2018 18:28:38 -0000 Content-Type: text/plain; charset="UTF-8" On 16 February 2018 at 17:00, Leif Lindholm wrote: > On Thu, Feb 15, 2018 at 05:20:50PM +0000, Ard Biesheuvel wrote: >> Add a node for the SPI controller to the device tree so the OS may >> attach to it. This is the SPI controller that is attached to the >> 96boards mezzanine connector on Developer Box. > > Just a generic question (which also applies to the subsequent patch): > Are there any implications here with regards to this bus running in > master or slave mode? > Not really, since that depends entirely on the OS. We just assert the presence of a certain IP block at a certain memory offset, and whether the hardware supports slave mode is left unspecified. Whether the OS supports slave mode (for this particular IP block) is not a property of the hardware. >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel >> --- >> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 18 ++++++++++++++++++ >> 1 file changed, 18 insertions(+) >> >> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> index 9085adb326ab..ba445a50f16f 100644 >> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> @@ -538,4 +538,22 @@ >> clock-names = "core", "iface"; >> dma-coherent; >> }; >> + >> + clk_alw_1_8: spi_ihclk { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-frequency = <125000000>; >> + clock-output-names = "iHCLK"; >> + }; >> + >> + spi: spi@54810000 { >> + compatible = "socionext,synquacer-spi"; >> + reg = <0x0 0x54810000 0x0 0x1000>; >> + clocks = <&clk_alw_1_8>; >> + clock-names = "iHCLK"; >> + socionext,use-rtm; >> + socionext,set-aces; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> }; >> -- >> 2.11.0 >>