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From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: Vabhav Sharma <vabhav.sharma@nxp.com>, "Cohen, Eugene" <eugene@hp.com>
Cc: "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Subject: Re: SError Exception and HCR_EL2 Usage
Date: Mon, 9 Oct 2017 20:15:41 +0100	[thread overview]
Message-ID: <CAKv+Gu8qTPAQPv-MFYL7OE0kqFNNDos+8KZHR39WfrV1aspu-w@mail.gmail.com> (raw)
In-Reply-To: <DB4PR04MB299F2A707A0990558BC87D0F3740@DB4PR04MB299.eurprd04.prod.outlook.com>

On 9 October 2017 at 18:33, Vabhav Sharma <vabhav.sharma@nxp.com> wrote:
> Dear Experts,
>
> I am facing SError exception during UEFI bring-up.
> At boot , secure f/w starts in EL3 and loads UEFI image to DDR. After this secure f/w passes control to UEFI in EL2.
>
> I debugged and manifest the problem by adding below lines in UEFI PrePi entry point(ModuleEntryPoint.S)
>
> ASM_FUNC(_ModuleEntryPoint)
>
> +msr  daifclr,#4
>
> +isb
>
> +mrs x0, hcr_el2
>
> +ldr x1, =0x08000000
>
> +orr x0, x0, x1
>
> +msr hcr_el2, x0
>
> +isb
>
>
>
> Once exception occurs than ELR_EL2 point to 'isb' instruction and ESR_EL2 is SError Exception syndrome.
>
> Could you please suggest if this is UEFI problem or Secure f/w issue?
>

As I said before, if the SError hits as soon as you unmask it in EL2
(which appears what you are doing as the very first instruction when
entering EL2), it is very unlikely that it was triggered by code
running at EL2.

> Additionally, TGE bit is set in hcr_el2 three times during PrePei phase(ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c),DxeMain(),ArmCpuDxe.
> Please explain the purpose of setting it or require to be fixed?
>

IIRC this was added following a discussion with Eugene.

Eugene, do you remember the details? I think the general idea is that
no exceptions should be routed to EL1 before EL2 has had the chance of
setting it up.


      reply	other threads:[~2017-10-09 19:12 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-09 17:33 SError Exception and HCR_EL2 Usage Vabhav Sharma
2017-10-09 19:15 ` Ard Biesheuvel [this message]

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