From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::229; helo=mail-io0-x229.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x229.google.com (mail-io0-x229.google.com [IPv6:2607:f8b0:4001:c06::229]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8A31621F3C198 for ; Mon, 9 Oct 2017 12:12:15 -0700 (PDT) Received: by mail-io0-x229.google.com with SMTP id f20so3309441ioj.9 for ; Mon, 09 Oct 2017 12:15:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=4p5o1z35qrEOxkK47MY9O9pfpjx8mfuLVZYgYMLr5Es=; b=V2HaSokfGmRT8FQBiGDur9lXPWeZ5eQRVB+cmKw8zI93hHk8oJaTLgZSUsyIflDUvF lhqb9h7CS5IknAg4GGi19FP7b8f0/LehswoyAE/t1R24SrqxC3yW5gIP+oxlzp+/3X0q yJW7hW/HjuWlMMz+vZgzS2eAe8FmPiw3I/8Y0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=4p5o1z35qrEOxkK47MY9O9pfpjx8mfuLVZYgYMLr5Es=; b=Ww13zs7EYn67YYHLHI4uspObLaPt8aGvVG12OFFryzwRti3i+1UN5Sxb2SL7cpFz1s BUIjAqPI2/fFFcO5R1aV9jZhvPd1RdbJRx5w+KhEfMq267hz8KJcV279OJaWRqE6B2Ai ZXDLxhju8JIsXUUFr42LTFOKj05dipK9Fnn6D4zvHcWglYaoLF442pBSfhiFcXkutm2p PbUVDrTHSipIuETqyWfg0QNfLRUWKDaA7G/B4bPA+xp2yE8ZjzgQa6IVi55UjtZi1OP5 Ej/NyoUzefN3f2DNG6e2FJdP6brGiD+3C94PQ8OQTibWL3Zlnby8U2VwcNvAkFYhMNDw BAZw== X-Gm-Message-State: AMCzsaU/pPFhh4CyWLUKtRZTsOi44Jq+k9JYRQVE1A7DrGDRslpggp8F c/jC30ZiEkRDggN/Z4dHy1Mun8onjN3t75XQ060WIQ== X-Google-Smtp-Source: AOwi7QDMuAOhPqVns/t3VSMNrFTlpIQheYEbgk0HheuOKyrCmTZcji71ZKCwN/+I0uWMwC76myiSCZgDkzehczUQ6Xw= X-Received: by 10.107.154.138 with SMTP id c132mr8967173ioe.95.1507576542375; Mon, 09 Oct 2017 12:15:42 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.131.167 with HTTP; Mon, 9 Oct 2017 12:15:41 -0700 (PDT) In-Reply-To: References: From: Ard Biesheuvel Date: Mon, 9 Oct 2017 20:15:41 +0100 Message-ID: To: Vabhav Sharma , "Cohen, Eugene" Cc: "edk2-devel@lists.01.org" Subject: Re: SError Exception and HCR_EL2 Usage X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Oct 2017 19:12:15 -0000 Content-Type: text/plain; charset="UTF-8" On 9 October 2017 at 18:33, Vabhav Sharma wrote: > Dear Experts, > > I am facing SError exception during UEFI bring-up. > At boot , secure f/w starts in EL3 and loads UEFI image to DDR. After this secure f/w passes control to UEFI in EL2. > > I debugged and manifest the problem by adding below lines in UEFI PrePi entry point(ModuleEntryPoint.S) > > ASM_FUNC(_ModuleEntryPoint) > > +msr daifclr,#4 > > +isb > > +mrs x0, hcr_el2 > > +ldr x1, =0x08000000 > > +orr x0, x0, x1 > > +msr hcr_el2, x0 > > +isb > > > > Once exception occurs than ELR_EL2 point to 'isb' instruction and ESR_EL2 is SError Exception syndrome. > > Could you please suggest if this is UEFI problem or Secure f/w issue? > As I said before, if the SError hits as soon as you unmask it in EL2 (which appears what you are doing as the very first instruction when entering EL2), it is very unlikely that it was triggered by code running at EL2. > Additionally, TGE bit is set in hcr_el2 three times during PrePei phase(ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c),DxeMain(),ArmCpuDxe. > Please explain the purpose of setting it or require to be fixed? > IIRC this was added following a discussion with Eugene. Eugene, do you remember the details? I think the general idea is that no exceptions should be routed to EL1 before EL2 has had the chance of setting it up.