From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::243; helo=mail-it0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x243.google.com (mail-it0-x243.google.com [IPv6:2607:f8b0:4001:c0b::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6EC59211F886D for ; Tue, 26 Jun 2018 11:21:06 -0700 (PDT) Received: by mail-it0-x243.google.com with SMTP id 188-v6so3656630ita.5 for ; Tue, 26 Jun 2018 11:21:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=vjo9KN7aRVfrMa7nR6suRHKSFVtle5YMHBqVc0hMBnQ=; b=QdIRiXyCqJ7VlUtgOLPENs+7FPyYB4Pa+I7iczMXKVrkc1YH1lx5rhiBC/q2Fdqo32 a99uMuqMEhJ79hjq2VvfrKG3XeuRAErzmlyS90TnXwsC8U+Q0kTcKR/OAqjgWCw39s/V miUJVW+LltLviLGOI1VH/2Yhi2y3ocomtg3zQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=vjo9KN7aRVfrMa7nR6suRHKSFVtle5YMHBqVc0hMBnQ=; b=rqP31IKa9RGVCFc1UJ+EzyxNOMtLjItk69EgWk2rLWpeNycA3qX7262XC2VQ8uOGoF 12QqCcDw1nfIRrOU50qP8xZtwggTiBbvR4Q+IZKpNCBo2kP3d8v3LZuRXApXHmehFt0v UgRHH7poxVd8mhA8sxewj9MNRtZlCPEKVlrh33J63fCwgTyb/7OtDqld8KJx1Yra6iBx Nq9CjIpLoMk3V8gpEuPslqOssnMInGezrXzhHoyemppzTv4L5ByTCvDEeh6dfmLvv+N7 KHnVEWmP2XXosKCCrth8JJJxcBpr4zsMKIQm3XiEZlfw60s+xqjhj3zkMhBG0c3vAVzB MXqg== X-Gm-Message-State: APt69E0pYsJKf3bu+V4iEP6dBZ0wjoTzwC4chGgMtYUWQ+jO7obwiYKI RugZtDfXbwuYiTZRk02kZ259OBCwEkyNKd04OIlJqw== X-Google-Smtp-Source: AAOMgpfe9s6nnnOdjKP5dsVXXNtHa6YO87sVrkQLxzb+Q0sStyate37RQkn+rkYhch3921bUimsIXXBAOkQ6QNliJts= X-Received: by 2002:a24:3105:: with SMTP id y5-v6mr2371616ity.138.1530037265400; Tue, 26 Jun 2018 11:21:05 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:bbc7:0:0:0:0:0 with HTTP; Tue, 26 Jun 2018 11:21:04 -0700 (PDT) In-Reply-To: <20180626143426.b2bsv7hdjkjv7znd@bivouac.eciton.net> References: <20180626104424.3524-1-ard.biesheuvel@linaro.org> <20180626104424.3524-2-ard.biesheuvel@linaro.org> <20180626142409.gwn6daatv3vbnqxe@bivouac.eciton.net> <20180626143426.b2bsv7hdjkjv7znd@bivouac.eciton.net> From: Ard Biesheuvel Date: Tue, 26 Jun 2018 20:21:04 +0200 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" Subject: Re: [PATCH edk2-platforms 1/2] Silicon/SynQuacer: add preliminary support for PCIe MMIO32 translation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jun 2018 18:21:06 -0000 Content-Type: text/plain; charset="UTF-8" On 26 June 2018 at 16:34, Leif Lindholm wrote: > On Tue, Jun 26, 2018 at 04:25:46PM +0200, Ard Biesheuvel wrote: >> On 26 June 2018 at 16:24, Leif Lindholm wrote: >> > On Tue, Jun 26, 2018 at 12:44:23PM +0200, Ard Biesheuvel wrote: >> >> Add the basic support for enabling PCIe MMIO32 translation on the >> >> SynQuacer, without actually enabling it just yet. It would allow us >> >> to increase the bus range to 255 MB [from 127 MB] and the MMIO32 >> >> range to 512 MB or more [from 128 MB], but it is more likely to >> >> cause compatibility issues with code ported from the PC platform. >> >> >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> >> Signed-off-by: Ard Biesheuvel >> >> --- >> >> Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl | 8 ++++---- >> >> Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 2 ++ >> >> Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 6 ++++-- >> >> Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 2 +- >> >> 4 files changed, 11 insertions(+), 7 deletions(-) >> >> >> >> diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl >> >> index 51e9d0b22c3d..77d4763d1a85 100644 >> >> --- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl >> >> +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl >> >> @@ -86,14 +86,14 @@ DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR", >> >> SYNQUACER_PCI_SEG0_BUSNUM_RANGE // RangeLength - # of Busses >> >> ) >> >> >> >> - DWordMemory ( // 32-bit BAR Windows >> >> + QWordMemory ( // 32-bit BAR Windows >> >> ResourceProducer, PosDecode, >> >> MinFixed, MaxFixed, >> >> Cacheable, ReadWrite, >> >> 0x00000000, // Granularity >> >> SYNQUACER_PCI_SEG0_MMIO32_MIN, // Min Base Address >> >> SYNQUACER_PCI_SEG0_MMIO32_MAX, // Max Base Address >> >> - 0x00000000, // Translate >> >> + SYNQUACER_PCI_SEG0_MMIO32_XLATE, // Translate >> >> SYNQUACER_PCI_SEG0_MMIO32_SIZE // Length >> >> ) >> >> >> >> @@ -224,14 +224,14 @@ DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR", >> >> SYNQUACER_PCI_SEG1_BUSNUM_RANGE // RangeLength - # of Busses >> >> ) >> >> >> >> - DWordMemory ( // 32-bit BAR Windows >> >> + QWordMemory ( // 32-bit BAR Windows >> >> ResourceProducer, PosDecode, >> >> MinFixed, MaxFixed, >> >> Cacheable, ReadWrite, >> >> 0x00000000, // Granularity >> >> SYNQUACER_PCI_SEG1_MMIO32_MIN, // Min Base Address >> >> SYNQUACER_PCI_SEG1_MMIO32_MAX, // Max Base Address >> >> - 0x00000000, // Translate >> >> + SYNQUACER_PCI_SEG1_MMIO32_XLATE, // Translate >> >> SYNQUACER_PCI_SEG1_MMIO32_SIZE // Length >> >> ) >> >> >> >> diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h >> >> index 950cece13e81..798f59db2a94 100644 >> >> --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h >> >> +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h >> >> @@ -34,6 +34,7 @@ >> >> #define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x68000000 >> >> #define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fffffff >> >> #define SYNQUACER_PCI_SEG0_MMIO32_SIZE 0x08000000 >> >> +#define SYNQUACER_PCI_SEG0_MMIO32_XLATE 0x0 >> >> >> >> #define SYNQUACER_PCI_SEG0_MMIO64_MIN 0x3e00000000 >> >> #define SYNQUACER_PCI_SEG0_MMIO64_MAX 0x3effffffff >> >> @@ -57,6 +58,7 @@ >> >> #define SYNQUACER_PCI_SEG1_MMIO32_MIN 0x78000000 >> >> #define SYNQUACER_PCI_SEG1_MMIO32_MAX 0x7fffffff >> >> #define SYNQUACER_PCI_SEG1_MMIO32_SIZE 0x08000000 >> >> +#define SYNQUACER_PCI_SEG1_MMIO32_XLATE 0x0 >> >> >> >> #define SYNQUACER_PCI_SEG1_MMIO64_MIN 0x3f00000000 >> >> #define SYNQUACER_PCI_SEG1_MMIO64_MAX 0x3fffffffff >> >> diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c >> >> index 341939876bd3..7c096f0801dd 100644 >> >> --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c >> >> +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c >> >> @@ -107,7 +107,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = { >> >> SYNQUACER_PCI_SEG0_PORTIO_MAX, >> >> MAX_UINT64 - SYNQUACER_PCI_SEG0_PORTIO_OFFSET + 1 }, // Io >> >> { SYNQUACER_PCI_SEG0_MMIO32_MIN, >> >> - SYNQUACER_PCI_SEG0_MMIO32_MAX }, // Mem >> >> + SYNQUACER_PCI_SEG0_MMIO32_MAX, >> >> + MAX_UINT64 - SYNQUACER_PCI_SEG0_MMIO32_XLATE + 1 }, // Mem >> > >> > So, this had me scratching my head for a second. >> > I may get pickier about requring explicitly initializing the >> > Translation field in future, but for this patch: >> > Reviewed-by: Leif Lindholm >> > >> >> That field did not exist yet when this code was merged. It was >> introduced by Heyi's recent PCI patches. > > Ah, fair enough. > Slightly unfortunate C just silently lets that through though... > > / > Leif > Pushed as 3165d24e0c85..5ed298efba3b Thanks >> >> { SYNQUACER_PCI_SEG0_MMIO64_MIN, >> >> SYNQUACER_PCI_SEG0_MMIO64_MAX }, // MemAbove4G >> >> { MAX_UINT64, 0x0 }, // PMem >> >> @@ -127,7 +128,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = { >> >> SYNQUACER_PCI_SEG1_PORTIO_MAX, >> >> MAX_UINT64 - SYNQUACER_PCI_SEG1_PORTIO_OFFSET + 1 }, // Io >> >> { SYNQUACER_PCI_SEG1_MMIO32_MIN, >> >> - SYNQUACER_PCI_SEG1_MMIO32_MAX }, // Mem >> >> + SYNQUACER_PCI_SEG1_MMIO32_MAX, >> >> + MAX_UINT64 - SYNQUACER_PCI_SEG1_MMIO32_XLATE + 1 }, // Mem >> >> { SYNQUACER_PCI_SEG1_MMIO64_MIN, >> >> SYNQUACER_PCI_SEG1_MMIO64_MAX }, // MemAbove4G >> >> { MAX_UINT64, 0x0 }, // PMem >> >> diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c >> >> index 227f9a725ce8..75a663e974e1 100644 >> >> --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c >> >> +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c >> >> @@ -322,7 +322,7 @@ PciInitControllerPost ( >> >> >> >> // Region 0: MMIO32 range >> >> ConfigureWindow (DbiBase, 0, >> >> - RootBridge->Mem.Base, >> >> + RootBridge->Mem.Base - RootBridge->Mem.Translation, >> >> RootBridge->Mem.Base, >> >> RootBridge->Mem.Limit - RootBridge->Mem.Base + 1, >> >> IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | >> >> -- >> >> 2.17.1 >> >>