From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi0-x230.google.com (mail-oi0-x230.google.com [IPv6:2607:f8b0:4003:c06::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 48C451A1DFE for ; Fri, 9 Sep 2016 03:41:34 -0700 (PDT) Received: by mail-oi0-x230.google.com with SMTP id m11so132512143oif.1 for ; Fri, 09 Sep 2016 03:41:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=0pjcorsPqsUlyeuavREmGUkZEk/F5RktQimOLd7qHBo=; b=AxpNmRaf28Vi8re78THBRj2jPamAymrLBF+Bhl3K4lGzcgkkYUHuQFwSig7fsNQorB 4gYvmQgb2WjwLwI+mABrVaiBgiD8PZi2Mlf35IYeKStp8wcYekSnAtM+nbKzcyiKpW5a ATZGrMTQZcG1gwUQ19Gpgf4UiiH+MrdNNv0DY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=0pjcorsPqsUlyeuavREmGUkZEk/F5RktQimOLd7qHBo=; b=FDMbpvpdDIxRvYTMVP89kdWyRy16w2G10J8PIV1Z203TD+VdOhRsSfPgFWgVqcMnTt hEPdRJOlSmy8AE0YfnGmou7DwRuRebq0itr/rSWWFr/XSBs3heaxivMhuwVbAmKj/fp6 q9/+YGSZm4RpoYaRy1AJMxV0JZFqdgqUnPUfhj24cMz0zna7rYNxuJGjrHkBFJcDIHbl n0hGiRSflyZ2J5GZzaJaP3lFM8YDOdgmOSX0ngiIYyu16pJikoZi/UajFE/v+UsDxsNV iYK7mbhY8kVRzlIxZ7+4XcBa0azz/d39DydR261sTwPUJMoQCBTC7BeQgs/99qvF1pw8 Vohg== X-Gm-Message-State: AE9vXwPWfrJPYDEX24c9QnBQCsHUiZ1QVwPnxlxHER0+fvKgxEY3P18NgK4OMkWf/L8Fm+vldsMwNEwY7a3Ddgrd X-Received: by 10.157.61.166 with SMTP id l35mr4227233otc.52.1473417693589; Fri, 09 Sep 2016 03:41:33 -0700 (PDT) MIME-Version: 1.0 Received: by 10.36.204.195 with HTTP; Fri, 9 Sep 2016 03:41:33 -0700 (PDT) In-Reply-To: <1473408424-17833-1-git-send-email-ard.biesheuvel@linaro.org> References: <1473408424-17833-1-git-send-email-ard.biesheuvel@linaro.org> From: Ard Biesheuvel Date: Fri, 9 Sep 2016 11:41:33 +0100 Message-ID: To: edk2-devel-01 , Leif Lindholm , "Cohen, Eugene" Cc: Ard Biesheuvel Subject: Re: [PATCH] ArmPkg/ArmMmuLib: base page table VA size on GCD memory map size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Sep 2016 10:41:34 -0000 Content-Type: text/plain; charset=UTF-8 Please disregard, I will follow up with a proper series On 9 September 2016 at 09:07, Ard Biesheuvel wrote: > As reported by Eugene, the practice of sizing the address space in the > virtual memory system based on the maximum address in the table passed > to ArmConfigureMmu() is problematic, since it fails to take into account > the fact that the GCD memory space may be extended at a later time, both > for memory and for MMIO. So instead, choose the VA size identical to the > GCD memory map size, which is based on PcdPrePiCpuMemorySize on ARM > systems. > > Reported-by: Eugene Cohen > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel > --- > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 14 ++------------ > ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 4 ++++ > ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf | 4 ++++ > 3 files changed, 10 insertions(+), 12 deletions(-) > > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > index 6e05e6085011..b5900a761f80 100644 > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > @@ -582,9 +582,7 @@ ArmConfigureMmu ( > VOID* TranslationTable; > UINTN TranslationTablePageCount; > UINT32 TranslationTableAttribute; > - ARM_MEMORY_REGION_DESCRIPTOR *MemoryTableEntry; > UINT64 MaxAddress; > - UINT64 TopAddress; > UINTN T0SZ; > UINTN RootTableEntryCount; > UINT64 TCR; > @@ -595,16 +593,8 @@ ArmConfigureMmu ( > return RETURN_INVALID_PARAMETER; > } > > - // Identify the highest address of the memory table > - MaxAddress = MemoryTable->PhysicalBase + MemoryTable->Length - 1; > - MemoryTableEntry = MemoryTable; > - while (MemoryTableEntry->Length != 0) { > - TopAddress = MemoryTableEntry->PhysicalBase + MemoryTableEntry->Length - 1; > - if (TopAddress > MaxAddress) { > - MaxAddress = TopAddress; > - } > - MemoryTableEntry++; > - } > + // Cover the entire GCD memory space > + MaxAddress = (1UL << PcdGet8 (PcdPrePiCpuMemorySize)) - 1; > > // Lookup the Table Level to get the information > LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount); > diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf > index 1533c2944e8e..b9f264de8d26 100644 > --- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf > +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf > @@ -32,6 +32,7 @@ [Sources.ARM] > > [Packages] > ArmPkg/ArmPkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > MdePkg/MdePkg.dec > > [LibraryClasses] > @@ -39,5 +40,8 @@ [LibraryClasses] > CacheMaintenanceLib > MemoryAllocationLib > > +[Pcd.AARCH64] > + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize > + > [Pcd.ARM] > gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride > diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf b/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf > index 14ebf8de673d..ecf13f790734 100644 > --- a/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf > +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf > @@ -28,9 +28,13 @@ [Sources.AARCH64] > > [Packages] > ArmPkg/ArmPkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > MdePkg/MdePkg.dec > > [LibraryClasses] > ArmLib > CacheMaintenanceLib > MemoryAllocationLib > + > +[Pcd.AARCH64] > + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize > -- > 2.7.4 >