* [PATCH v2 00/13] EDK2 spring cleaning -- OpenPlatformPkg edition
@ 2017-03-31 14:15 Ard Biesheuvel
2017-03-31 14:15 ` [PATCH v2 01/13] Platforms/VExpress: remove unused logo PCD Ard Biesheuvel
` (9 more replies)
0 siblings, 10 replies; 15+ messages in thread
From: Ard Biesheuvel @ 2017-03-31 14:15 UTC (permalink / raw)
To: edk2-devel, leif.lindholm, ryan.harkin; +Cc: Ard Biesheuvel
This is the OpenPlatformPkg counterpart of the series
ArmPlatformgPkg spring cleaning -- now includes Juno [v2]
sent out out roughly the same time as this one. Note that they are inter-
dependent, i.e., applying one without the other will not result in a
working build.
Changes since v1:
- add cleanup patches for Juno as well, including a switch to the generic
PCI host bridge driver
- patches are updated to account for the API change in DtPlatformDxe -- the
platform glue is now provided by DtPlatformDtbLoaderLib implementations
- use existing copies of VExpress dtb images
Ard Biesheuvel (13):
Platforms/VExpress: remove unused logo PCD
Platforms/VExpress: remove unused StatusCode references
Platforms/VExpress: get rid of Tiano compression
Platforms/VExpress: remove BdsLib library class resolutions
Platforms/TC2: move to new DtPlatformDxe driver
Platforms/FVP: add DtPlatformDtbLoaderLib implementation
Platforms/FVP-AArch64: switch to simpler DT platform driver
Platforms/Juno: add non-discoverable device driver and library
Platforms/Juno: add PciHostBridgeLib implementation
Platforms/Juno: switch to generic PCI host bridge driver
Platforms/Juno: remove BdsLib dependency
Platforms/Juno: add DtPlatformDtbLoaderLib implementation
Platforms/Juno: switch to DtPlatformDxe
Platforms/ARM/Juno/ArmJuno.dsc | 39 +-
Platforms/ARM/Juno/ArmJuno.fdf | 31 +-
Platforms/ARM/Juno/DeviceTree/juno-r1.dtb | Bin 0 -> 23627 bytes
Platforms/ARM/Juno/DeviceTree/juno-r2.dtb | Bin 0 -> 23627 bytes
Platforms/ARM/Juno/DeviceTree/juno.dtb | Bin 0 -> 22431 bytes
Platforms/ARM/Juno/Library/JunoDtPlatformDtbLoaderLib/JunoDtPlatformDtbLoaderLib.c | 71 +++
Platforms/ARM/Juno/Library/JunoDtPlatformDtbLoaderLib/JunoDtPlatformDtbLoaderLib.inf | 38 ++
Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c | 185 ++++++
Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf | 77 +++
Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.c | 191 ++++++
Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.h | 107 ++++
Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc | 22 +-
Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf | 27 +-
Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 33 +-
Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf | 54 +-
Platforms/ARM/VExpress/ArmVExpress.dsc.inc | 24 +-
Platforms/ARM/VExpress/DeviceTree/vexpress-v2m-rs1.dtsi | 442 +++++++++++++
Platforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dtb | Bin 0 -> 19070 bytes
Platforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dts | 659 ++++++++++++++++++++
Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.c | 134 ++++
Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.inf | 39 ++
21 files changed, 2025 insertions(+), 148 deletions(-)
create mode 100644 Platforms/ARM/Juno/DeviceTree/juno-r1.dtb
create mode 100644 Platforms/ARM/Juno/DeviceTree/juno-r2.dtb
create mode 100644 Platforms/ARM/Juno/DeviceTree/juno.dtb
create mode 100644 Platforms/ARM/Juno/Library/JunoDtPlatformDtbLoaderLib/JunoDtPlatformDtbLoaderLib.c
create mode 100644 Platforms/ARM/Juno/Library/JunoDtPlatformDtbLoaderLib/JunoDtPlatformDtbLoaderLib.inf
create mode 100644 Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c
create mode 100644 Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf
create mode 100644 Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.c
create mode 100644 Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.h
create mode 100644 Platforms/ARM/VExpress/DeviceTree/vexpress-v2m-rs1.dtsi
create mode 100644 Platforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dtb
create mode 100644 Platforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dts
create mode 100644 Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.c
create mode 100644 Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.inf
--
2.9.3
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v2 01/13] Platforms/VExpress: remove unused logo PCD 2017-03-31 14:15 [PATCH v2 00/13] EDK2 spring cleaning -- OpenPlatformPkg edition Ard Biesheuvel @ 2017-03-31 14:15 ` Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 02/13] Platforms/VExpress: remove unused StatusCode references Ard Biesheuvel ` (8 subsequent siblings) 9 siblings, 0 replies; 15+ messages in thread From: Ard Biesheuvel @ 2017-03-31 14:15 UTC (permalink / raw) To: edk2-devel, leif.lindholm, ryan.harkin; +Cc: Ard Biesheuvel This file and associated PCD are no longer used by our BDS code, so remove them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf | 7 ------- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf | 7 ------- 2 files changed, 14 deletions(-) diff --git a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf index 90746158351e..5c3a2316cb68 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf +++ b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf @@ -175,13 +175,6 @@ FvNameGuid = 73dcb643-3862-4904-9076-a94af1890243 INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf INF MdeModulePkg/Application/UiApp/UiApp.inf - # - # TianoCore logo (splash screen) - # - FILE FREEFORM = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) { - SECTION RAW = MdeModulePkg/Logo/Logo.bmp - } - # FV Filesystem INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf index 2ace4d8e04c3..81966d2c3bce 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf @@ -167,13 +167,6 @@ FvNameGuid = 87940482-fc81-41c3-87e6-399cf85ac8a0 INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf INF MdeModulePkg/Application/UiApp/UiApp.inf - # - # TianoCore logo (splash screen) - # - FILE FREEFORM = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) { - SECTION RAW = MdeModulePkg/Logo/Logo.bmp - } - # FV Filesystem INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf -- 2.9.3 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 02/13] Platforms/VExpress: remove unused StatusCode references 2017-03-31 14:15 [PATCH v2 00/13] EDK2 spring cleaning -- OpenPlatformPkg edition Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 01/13] Platforms/VExpress: remove unused logo PCD Ard Biesheuvel @ 2017-03-31 14:15 ` Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 03/13] Platforms/VExpress: get rid of Tiano compression Ard Biesheuvel ` (7 subsequent siblings) 9 siblings, 0 replies; 15+ messages in thread From: Ard Biesheuvel @ 2017-03-31 14:15 UTC (permalink / raw) To: edk2-devel, leif.lindholm, ryan.harkin; +Cc: Ard Biesheuvel We never use the status code facility, so remove the libraries and other references to it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 1 - Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf | 1 - Platforms/ARM/VExpress/ArmVExpress.dsc.inc | 11 ++--------- 3 files changed, 2 insertions(+), 11 deletions(-) diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc index 56feed48495f..f76893626e08 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc @@ -209,7 +209,6 @@ ArmPlatformPkg/PlatformPei/PlatformPeim.inf ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf ArmPkg/Drivers/CpuPei/CpuPei.inf - IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf Nt32Pkg/BootModePei/BootModePei.inf MdeModulePkg/Universal/Variable/Pei/VariablePei.inf MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf index 81966d2c3bce..fbf8e9b30c0e 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf @@ -229,7 +229,6 @@ READ_LOCK_STATUS = TRUE INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf INF ArmPkg/Drivers/CpuPei/CpuPei.inf INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf - INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf !endif diff --git a/Platforms/ARM/VExpress/ArmVExpress.dsc.inc b/Platforms/ARM/VExpress/ArmVExpress.dsc.inc index fdd5341971b7..aed889747b2e 100644 --- a/Platforms/ARM/VExpress/ArmVExpress.dsc.inc +++ b/Platforms/ARM/VExpress/ArmVExpress.dsc.inc @@ -155,6 +155,8 @@ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf + [LibraryClasses.common.SEC] ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf @@ -182,7 +184,6 @@ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf @@ -197,7 +198,6 @@ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf @@ -214,14 +214,12 @@ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf - ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf [LibraryClasses.common.DXE_DRIVER] - ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf @@ -234,12 +232,10 @@ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf # UiApp dependencies - ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf [LibraryClasses.common.UEFI_DRIVER] - ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf @@ -249,7 +245,6 @@ [LibraryClasses.common.DXE_RUNTIME_DRIVER] HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf - ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigRuntimeLib/ArmVExpressSysConfigRuntimeLib.inf !if $(SECURE_BOOT_ENABLE) == TRUE @@ -366,8 +361,6 @@ # DEBUG_ERROR 0x80000000 // Error gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 - gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|"" gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07 gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000 -- 2.9.3 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 03/13] Platforms/VExpress: get rid of Tiano compression 2017-03-31 14:15 [PATCH v2 00/13] EDK2 spring cleaning -- OpenPlatformPkg edition Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 01/13] Platforms/VExpress: remove unused logo PCD Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 02/13] Platforms/VExpress: remove unused StatusCode references Ard Biesheuvel @ 2017-03-31 14:15 ` Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 04/13] Platforms/VExpress: remove BdsLib library class resolutions Ard Biesheuvel ` (6 subsequent siblings) 9 siblings, 0 replies; 15+ messages in thread From: Ard Biesheuvel @ 2017-03-31 14:15 UTC (permalink / raw) To: edk2-devel, leif.lindholm, ryan.harkin; +Cc: Ard Biesheuvel There are some references to Tiano compression and to libraries that implement it, but we never use it. So get rid of it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/ARM/Juno/ArmJuno.fdf | 9 --------- Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf | 9 --------- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf | 9 --------- Platforms/ARM/VExpress/ArmVExpress.dsc.inc | 5 ----- 4 files changed, 32 deletions(-) diff --git a/Platforms/ARM/Juno/ArmJuno.fdf b/Platforms/ARM/Juno/ArmJuno.fdf index beee7afd11fb..aadde45164a5 100644 --- a/Platforms/ARM/Juno/ArmJuno.fdf +++ b/Platforms/ARM/Juno/ArmJuno.fdf @@ -322,15 +322,6 @@ READ_LOCK_STATUS = TRUE UI STRING="$(MODULE_NAME)" Optional } -[Rule.Common.PEIM.TIANOCOMPRESSED] - FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - } - } - [Rule.Common.DXE_CORE] FILE DXE_CORE = $(NAMED_GUID) { PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi diff --git a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf index 5c3a2316cb68..1903389c8edd 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf +++ b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf @@ -265,15 +265,6 @@ READ_LOCK_STATUS = TRUE UI STRING="$(MODULE_NAME)" Optional } -[Rule.Common.PEIM.TIANOCOMPRESSED] - FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - } - } - [Rule.Common.DXE_CORE] FILE DXE_CORE = $(NAMED_GUID) { PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf index fbf8e9b30c0e..262515150dd9 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf @@ -286,15 +286,6 @@ READ_LOCK_STATUS = TRUE UI STRING="$(MODULE_NAME)" Optional } -[Rule.Common.PEIM.TIANOCOMPRESSED] - FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - } - } - [Rule.Common.DXE_CORE] FILE DXE_CORE = $(NAMED_GUID) { PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi diff --git a/Platforms/ARM/VExpress/ArmVExpress.dsc.inc b/Platforms/ARM/VExpress/ArmVExpress.dsc.inc index aed889747b2e..9dfe2ac9e440 100644 --- a/Platforms/ARM/VExpress/ArmVExpress.dsc.inc +++ b/Platforms/ARM/VExpress/ArmVExpress.dsc.inc @@ -186,7 +186,6 @@ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf - UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf @@ -201,7 +200,6 @@ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf - UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf @@ -215,7 +213,6 @@ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf - UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf @@ -226,7 +223,6 @@ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf [LibraryClasses.common.UEFI_APPLICATION] - UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf @@ -236,7 +232,6 @@ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf [LibraryClasses.common.UEFI_DRIVER] - UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf -- 2.9.3 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 04/13] Platforms/VExpress: remove BdsLib library class resolutions 2017-03-31 14:15 [PATCH v2 00/13] EDK2 spring cleaning -- OpenPlatformPkg edition Ard Biesheuvel ` (2 preceding siblings ...) 2017-03-31 14:15 ` [PATCH v2 03/13] Platforms/VExpress: get rid of Tiano compression Ard Biesheuvel @ 2017-03-31 14:15 ` Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 05/13] Platforms/TC2: move to new DtPlatformDxe driver Ard Biesheuvel ` (5 subsequent siblings) 9 siblings, 0 replies; 15+ messages in thread From: Ard Biesheuvel @ 2017-03-31 14:15 UTC (permalink / raw) To: edk2-devel, leif.lindholm, ryan.harkin; +Cc: Ard Biesheuvel ArmHwDxe and ArmFvpDxe no longer require a BdsLib library class resolution, so remove the explicit ones from the various .DSCs. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc | 5 +---- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 5 +---- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc index ae91a78d2dd8..55640837ba7c 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc @@ -244,10 +244,7 @@ # # Platform # - ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmHwDxe.inf { - <LibraryClasses> - BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf - } + ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmHwDxe.inf # # Filesystems diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc index f76893626e08..1b3c770da03f 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc @@ -292,10 +292,7 @@ # # Platform Driver # - ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf { - <LibraryClasses> - BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf - } + ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf OvmfPkg/VirtioBlkDxe/VirtioBlk.inf # -- 2.9.3 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 05/13] Platforms/TC2: move to new DtPlatformDxe driver 2017-03-31 14:15 [PATCH v2 00/13] EDK2 spring cleaning -- OpenPlatformPkg edition Ard Biesheuvel ` (3 preceding siblings ...) 2017-03-31 14:15 ` [PATCH v2 04/13] Platforms/VExpress: remove BdsLib library class resolutions Ard Biesheuvel @ 2017-03-31 14:15 ` Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 06/13] Platforms/FVP: add DtPlatformDtbLoaderLib implementation Ard Biesheuvel ` (4 subsequent siblings) 9 siblings, 0 replies; 15+ messages in thread From: Ard Biesheuvel @ 2017-03-31 14:15 UTC (permalink / raw) To: edk2-devel, leif.lindholm, ryan.harkin; +Cc: Ard Biesheuvel Replace the slightly overengineered FdtPlatformDxe driver with the new and simple DtPlatformDxe driver, which simply exposes a single builtin device tree binary to the OS. Note that this driver is configurable, i.e., it allows ACPI to be selected instead of device tree, in which case AcpiPlatformDxe is allowed to run. Note that this means we have to move the reference to FdtPlatformDxe.inf from the shared .DSC to the individual .DSCs for Juno and FVP that will keep using it for now. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/ARM/Juno/ArmJuno.dsc | 8 + Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc | 17 +- Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf | 13 +- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 8 + Platforms/ARM/VExpress/ArmVExpress.dsc.inc | 8 - Platforms/ARM/VExpress/DeviceTree/vexpress-v2m-rs1.dtsi | 442 +++++++++++++ Platforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dtb | Bin 0 -> 19070 bytes Platforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dts | 659 ++++++++++++++++++++ 8 files changed, 1133 insertions(+), 22 deletions(-) diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 1f56643ae996..71dc5463a84f 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -336,6 +336,14 @@ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf } + # + # FDT installation + # + EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf { + <LibraryClasses> + BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf + } + [Components.AARCH64] # # EBC diff --git a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc index 55640837ba7c..43856fe5c3ae 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc @@ -55,6 +55,8 @@ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf + [BuildOptions] !ifdef ARM_BIGLITTLE_TC2 *_*_ARM_ARCHCC_FLAGS = -DARM_BIGLITTLE_TC2=1 @@ -173,11 +175,6 @@ gEmbeddedTokenSpaceGuid.PcdLan9118DefaultNegotiationTimeout|400000 # - # Define the device path to the FDT for the platform - # - gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/ca15a7" - - # # ARM Architectural Timer Frequency # !ifdef ARM_BIGLITTLE_TC2 @@ -269,7 +266,15 @@ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { + <LibraryClasses> + NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf + } + + # + # FDT installation + # + EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf # # Bds diff --git a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf index 1903389c8edd..8bdde76a2ad5 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf +++ b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf @@ -181,14 +181,11 @@ FvNameGuid = 73dcb643-3862-4904-9076-a94af1890243 # # FDT installation # - # The UEFI driver is at the end of the list of the driver to be dispatched - # after the device drivers (eg: Ethernet) to ensure we have support for them. - INF EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf - - # Example to add a Device Tree to the Firmware Volume - #FILE FREEFORM = PCD(gArmVExpressTokenSpaceGuid.PcdFdtVExpressHwA15x2A7x3) { - # SECTION RAW = ArmPlatformPkg/ArmVExpressPkg/Fdts/vexpress-v2p-ca15_a7.dtb - #} + INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf + + FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { + SECTION RAW = OpenPlatformPkg/Platforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dtb + } [FV.FVMAIN_COMPACT] FvBaseAddress = 0xB0000000 diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc index 1b3c770da03f..e6778aafe8c6 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc @@ -315,3 +315,11 @@ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf } + + # + # FDT installation + # + EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf { + <LibraryClasses> + BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf + } diff --git a/Platforms/ARM/VExpress/ArmVExpress.dsc.inc b/Platforms/ARM/VExpress/ArmVExpress.dsc.inc index 9dfe2ac9e440..8c4de54c8875 100644 --- a/Platforms/ARM/VExpress/ArmVExpress.dsc.inc +++ b/Platforms/ARM/VExpress/ArmVExpress.dsc.inc @@ -491,14 +491,6 @@ MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf # - # FDT installation - # - EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf { - <LibraryClasses> - BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf - } - - # # UEFI application (Shell Embedded Boot Loader) # ShellPkg/Application/Shell/Shell.inf { diff --git a/Platforms/ARM/VExpress/DeviceTree/vexpress-v2m-rs1.dtsi b/Platforms/ARM/VExpress/DeviceTree/vexpress-v2m-rs1.dtsi new file mode 100644 index 000000000000..3086efacd00e --- /dev/null +++ b/Platforms/ARM/VExpress/DeviceTree/vexpress-v2m-rs1.dtsi @@ -0,0 +1,442 @@ +/* + * ARM Ltd. Versatile Express + * + * Motherboard Express uATX + * V2M-P1 + * + * HBI-0190D + * + * RS1 memory map ("ARM Cortex-A Series memory map" in the board's + * Technical Reference Manual) + * + * WARNING! The hardware described in this file is independent from the + * original variant (vexpress-v2m.dtsi), but there is a strong + * correspondence between the two configurations. + * + * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT + * CHANGES TO vexpress-v2m.dtsi! + */ + + motherboard { + model = "V2M-P1"; + arm,hbi = <0x190>; + arm,vexpress,site = <0>; + arm,v2m-memory-map = "rs1"; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; + }; + + psram@1,00000000 { + compatible = "arm,vexpress-psram", "mtd-ram"; + reg = <1 0x00000000 0x02000000>; + bank-width = <4>; + }; + + v2m_video_ram: vram@2,00000000 { + compatible = "arm,vexpress-vram"; + reg = <2 0x00000000 0x00800000>; + }; + + ethernet@2,02000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&v2m_fixed_3v3>; + vddvario-supply = <&v2m_fixed_3v3>; + }; + + usb@2,03000000 { + compatible = "nxp,usb-isp1761"; + reg = <2 0x03000000 0x20000>; + interrupts = <16>; + port1-otg; + }; + + iofpga@3,00000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysreg: sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + + v2m_led_gpios: sys_led { + compatible = "arm,vexpress-sysreg,sys_led"; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_mmc_gpios: sys_mci { + compatible = "arm,vexpress-sysreg,sys_mci"; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_flash_gpios: sys_flash { + compatible = "arm,vexpress-sysreg,sys_flash"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + v2m_sysctl: sysctl@020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; + }; + + /* PCI-E I2C bus */ + v2m_i2c_pcie: i2c@030000 { + compatible = "arm,versatile-i2c"; + reg = <0x030000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + pcie-switch@60 { + compatible = "idt,89hpes32h8"; + reg = <0x60>; + }; + }; + + aaci@040000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + mmci@050000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9 10>; + cd-gpios = <&v2m_mmc_gpios 0 0>; + wp-gpios = <&v2m_mmc_gpios 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@060000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@070000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: uart@090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&smbclk>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + /* DVI I2C bus */ + v2m_i2c_dvi: i2c@160000 { + compatible = "arm,versatile-i2c"; + reg = <0x160000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + dvi-transmitter@39 { + compatible = "sil,sii9022-tpi", "sil,sii9022"; + reg = <0x39>; + }; + + dvi-transmitter@60 { + compatible = "sil,sii9022-cpi", "sil,sii9022"; + reg = <0x60>; + }; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + compact-flash@1a0000 { + compatible = "arm,vexpress-cf", "ata-generic"; + reg = <0x1a0000 0x100 + 0x1a0100 0xf00>; + reg-shift = <2>; + }; + + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupt-names = "combined"; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&smbclk>; + clock-names = "clcdclk", "apb_pclk"; + memory-region = <&v2m_video_ram>; + max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */ + + port { + v2m_clcd_pads: endpoint { + remote-endpoint = <&v2m_clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + + panel { + compatible = "panel-dpi"; + + port { + v2m_clcd_panel: endpoint { + remote-endpoint = <&v2m_clcd_pads>; + }; + }; + + panel-timing { + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <40>; + hfront-porch = <24>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <2>; + }; + }; + }; + }; + + v2m_fixed_3v3: fixed-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + leds { + compatible = "gpio-leds"; + + user1 { + label = "v2m:green:user1"; + gpios = <&v2m_led_gpios 0 0>; + linux,default-trigger = "heartbeat"; + }; + + user2 { + label = "v2m:green:user2"; + gpios = <&v2m_led_gpios 1 0>; + linux,default-trigger = "mmc0"; + }; + + user3 { + label = "v2m:green:user3"; + gpios = <&v2m_led_gpios 2 0>; + linux,default-trigger = "cpu0"; + }; + + user4 { + label = "v2m:green:user4"; + gpios = <&v2m_led_gpios 3 0>; + linux,default-trigger = "cpu1"; + }; + + user5 { + label = "v2m:green:user5"; + gpios = <&v2m_led_gpios 4 0>; + linux,default-trigger = "cpu2"; + }; + + user6 { + label = "v2m:green:user6"; + gpios = <&v2m_led_gpios 5 0>; + linux,default-trigger = "cpu3"; + }; + + user7 { + label = "v2m:green:user7"; + gpios = <&v2m_led_gpios 6 0>; + linux,default-trigger = "cpu4"; + }; + + user8 { + label = "v2m:green:user8"; + gpios = <&v2m_led_gpios 7 0>; + linux,default-trigger = "cpu5"; + }; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + oscclk0 { + /* MCC static memory clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk0"; + }; + + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 65000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + v2m_oscclk2: oscclk2 { + /* IO FPGA peripheral clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <24000000 24000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk2"; + }; + + volt-vio { + /* Logic level voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VIO"; + regulator-always-on; + label = "VIO"; + }; + + temp-mcc { + /* MCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "MCC"; + }; + + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; diff --git a/Platforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dtb b/Platforms/ARM/VExpress/DeviceTree/vexpress-v2p-ca15_a7.dtb new file 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Versatile Express + * + * CoreTile Express A15x2 A7x3 + * Cortex-A15_A7 MPCore (V2P-CA15_A7) + * + * HBI-0249A + */ + +/dts-v1/; + +/ { + model = "V2P-CA15_CA7"; + arm,hbi = <0x249>; + arm,vexpress,site = <0xf>; + compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + i2c0 = &v2m_i2c_dvi; + i2c1 = &v2m_i2c_pcie; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + cci-control-port = <&cci_control1>; + cpu-idle-states = <&CLUSTER_SLEEP_BIG>; + capacity-dmips-mhz = <1024>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + cci-control-port = <&cci_control1>; + cpu-idle-states = <&CLUSTER_SLEEP_BIG>; + capacity-dmips-mhz = <1024>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + cci-control-port = <&cci_control2>; + cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz = <516>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + cci-control-port = <&cci_control2>; + cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz = <516>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + cci-control-port = <&cci_control2>; + cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + capacity-dmips-mhz = <516>; + }; + + idle-states { + CLUSTER_SLEEP_BIG: cluster-sleep-big { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2000>; + }; + + CLUSTER_SLEEP_LITTLE: cluster-sleep-little { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <500>; + min-residency-us = <2500>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + wdt@2a490000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0 0x2a490000 0 0x1000>; + interrupts = <0 98 4>; + clocks = <&oscclk6a>, <&oscclk6a>; + clock-names = "wdogclk", "apb_pclk"; + }; + + hdlcd@2b000000 { + compatible = "arm,hdlcd"; + reg = <0 0x2b000000 0 0x1000>; + interrupts = <0 85 4>; + clocks = <&hdlcd_clk>; + clock-names = "pxlclk"; + }; + + memory-controller@2b0a0000 { + compatible = "arm,pl341", "arm,primecell"; + reg = <0 0x2b0a0000 0 0x1000>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x2c001000 0 0x1000>, + <0 0x2c002000 0 0x2000>, + <0 0x2c004000 0 0x2000>, + <0 0x2c006000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + cci@2c090000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x2c090000 0 0x1000>; + ranges = <0x0 0x0 0x2c090000 0x10000>; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r0"; + reg = <0x9000 0x5000>; + interrupts = <0 105 4>, + <0 101 4>, + <0 102 4>, + <0 103 4>, + <0 104 4>; + }; + }; + + memory-controller@7ffd0000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0 0x7ffd0000 0 0x1000>; + interrupts = <0 86 4>, + <0 87 4>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + }; + + dma@7ff00000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0 0x7ff00000 0 0x1000>; + interrupts = <0 92 4>, + <0 88 4>, + <0 89 4>, + <0 90 4>, + <0 91 4>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + }; + + scc@7fff0000 { + compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; + reg = <0 0x7fff0000 0 0x1000>; + interrupts = <0 95 4>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + pmu_a15 { + compatible = "arm,cortex-a15-pmu"; + interrupts = <0 68 4>, + <0 69 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>; + }; + + pmu_a7 { + compatible = "arm,cortex-a7-pmu"; + interrupts = <0 128 4>, + <0 129 4>, + <0 130 4>; + interrupt-affinity = <&cpu2>, + <&cpu3>, + <&cpu4>; + }; + + oscclk6a: oscclk6a { + /* Reference 24MHz clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "oscclk6a"; + }; + + dcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + oscclk0 { + /* A15 PLL 0 reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <17000000 50000000>; + #clock-cells = <0>; + clock-output-names = "oscclk0"; + }; + + oscclk1 { + /* A15 PLL 1 reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <17000000 50000000>; + #clock-cells = <0>; + clock-output-names = "oscclk1"; + }; + + oscclk2 { + /* A7 PLL 0 reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <17000000 50000000>; + #clock-cells = <0>; + clock-output-names = "oscclk2"; + }; + + oscclk3 { + /* A7 PLL 1 reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 3>; + freq-range = <17000000 50000000>; + #clock-cells = <0>; + clock-output-names = "oscclk3"; + }; + + oscclk4 { + /* External AXI master clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 4>; + freq-range = <20000000 40000000>; + #clock-cells = <0>; + clock-output-names = "oscclk4"; + }; + + hdlcd_clk: oscclk5 { + /* HDLCD PLL reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 5>; + freq-range = <23750000 165000000>; + #clock-cells = <0>; + clock-output-names = "oscclk5"; + }; + + smbclk: oscclk6 { + /* Static memory controller clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 6>; + freq-range = <20000000 40000000>; + #clock-cells = <0>; + clock-output-names = "oscclk6"; + }; + + oscclk7 { + /* SYS PLL reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 7>; + freq-range = <17000000 50000000>; + #clock-cells = <0>; + clock-output-names = "oscclk7"; + }; + + oscclk8 { + /* DDR2 PLL reference clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 8>; + freq-range = <20000000 50000000>; + #clock-cells = <0>; + clock-output-names = "oscclk8"; + }; + + volt-a15 { + /* A15 CPU core voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "A15 Vcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + label = "A15 Vcore"; + }; + + volt-a7 { + /* A7 CPU core voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 1>; + regulator-name = "A7 Vcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + label = "A7 Vcore"; + }; + + amp-a15 { + /* Total current for the two A15 cores */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 0>; + label = "A15 Icore"; + }; + + amp-a7 { + /* Total current for the three A7 cores */ + compatible = "arm,vexpress-amp"; + arm,vexpress-sysreg,func = <3 1>; + label = "A7 Icore"; + }; + + temp-dcc { + /* DCC internal temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "DCC"; + }; + + power-a15 { + /* Total power for the two A15 cores */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 0>; + label = "A15 Pcore"; + }; + + power-a7 { + /* Total power for the three A7 cores */ + compatible = "arm,vexpress-power"; + arm,vexpress-sysreg,func = <12 1>; + label = "A7 Pcore"; + }; + + energy-a15 { + /* Total energy for the two A15 cores */ + compatible = "arm,vexpress-energy"; + arm,vexpress-sysreg,func = <13 0>, <13 1>; + label = "A15 Jcore"; + }; + + energy-a7 { + /* Total energy for the three A7 cores */ + compatible = "arm,vexpress-energy"; + arm,vexpress-sysreg,func = <13 2>, <13 3>; + label = "A7 Jcore"; + }; + }; + + etb@0,20010000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0x20010000 0 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + etb_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + + tpiu@0,20030000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0x20030000 0 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + tpiu_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + + replicator { + /* non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&funnel_out_port0>; + }; + }; + }; + }; + + funnel@0,20040000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x20040000 0 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel output port */ + port@0 { + reg = <0>; + funnel_out_port0: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + + /* funnel input ports */ + port@1 { + reg = <0>; + funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@2 { + reg = <1>; + funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&ptm1_out_port>; + }; + }; + + port@3 { + reg = <2>; + funnel_in_port2: endpoint { + slave-mode; + remote-endpoint = <&etm0_out_port>; + }; + }; + + /* Input port #3 is for ITM, not supported here */ + + port@4 { + reg = <4>; + funnel_in_port4: endpoint { + slave-mode; + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@5 { + reg = <5>; + funnel_in_port5: endpoint { + slave-mode; + remote-endpoint = <&etm2_out_port>; + }; + }; + }; + }; + + ptm@0,2201c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2201c000 0 0x1000>; + + cpu = <&cpu0>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + + ptm@0,2201d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2201d000 0 0x1000>; + + cpu = <&cpu1>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; + }; + }; + + etm@0,2203c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2203c000 0 0x1000>; + + cpu = <&cpu2>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + etm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port2>; + }; + }; + }; + + etm@0,2203d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2203d000 0 0x1000>; + + cpu = <&cpu3>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + etm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port4>; + }; + }; + }; + + etm@0,2203e000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2203e000 0 0x1000>; + + cpu = <&cpu4>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + etm2_out_port: endpoint { + remote-endpoint = <&funnel_in_port5>; + }; + }; + }; + + smb@08000000 { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "vexpress-v2m-rs1.dtsi" + }; + + site2: hsb@40000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x40000000 0x3fef0000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 3>; + interrupt-map = <0 0 &gic 0 36 4>, + <0 1 &gic 0 37 4>, + <0 2 &gic 0 38 4>, + <0 3 &gic 0 39 4>; + }; +}; -- 2.9.3 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 06/13] Platforms/FVP: add DtPlatformDtbLoaderLib implementation 2017-03-31 14:15 [PATCH v2 00/13] EDK2 spring cleaning -- OpenPlatformPkg edition Ard Biesheuvel ` (4 preceding siblings ...) 2017-03-31 14:15 ` [PATCH v2 05/13] Platforms/TC2: move to new DtPlatformDxe driver Ard Biesheuvel @ 2017-03-31 14:15 ` Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 07/13] Platforms/FVP-AArch64: switch to simpler DT platform driver Ard Biesheuvel ` (3 subsequent siblings) 9 siblings, 0 replies; 15+ messages in thread From: Ard Biesheuvel @ 2017-03-31 14:15 UTC (permalink / raw) To: edk2-devel, leif.lindholm, ryan.harkin; +Cc: Ard Biesheuvel In preparation of switching to DtPlatformDxe to supply the device tree image to the OS, add an implementation of DtPlatformDtbLoaderLib that loads the correct version from an FV. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.c | 134 ++++++++++++++++++++ Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.inf | 39 ++++++ 2 files changed, 173 insertions(+) diff --git a/Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.c b/Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.c new file mode 100644 index 000000000000..3a5613c83709 --- /dev/null +++ b/Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.c @@ -0,0 +1,134 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <PiDxe.h> + +#include <Library/ArmGicLib.h> +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/DxeServicesLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> + +#include "ArmPlatform.h" + +typedef enum { + ARM_FVP_BASE_AEMv8x4_AEMv8x4_GICV2, + ARM_FVP_BASE_AEMv8x4_AEMv8x4_GICV2_LEGACY, + ARM_FVP_BASE_AEMv8x4_AEMv8x4_GICV3, + ARM_FVP_FOUNDATION_GICV2, + ARM_FVP_FOUNDATION_GICV2_LEGACY, + ARM_FVP_FOUNDATION_GICV3, + ARM_FVP_UNKNOWN, +} ARM_VEXPRESS_PLATFORM_ID; + +ARM_VEXPRESS_PLATFORM_ID +GetPlatformId ( + VOID + ) +{ + UINT32 SysId; + UINT32 FvpSysId; + UINT32 VariantSysId; + ARM_GIC_ARCH_REVISION GicRevision; + + SysId = MmioRead32 (ARM_VE_SYS_ID_REG); + + // Remove the GIC variant to identify if we are running on the FVP Base or + // Foundation models + FvpSysId = SysId & (ARM_FVP_SYS_ID_HBI_MASK | ARM_FVP_SYS_ID_PLAT_MASK ); + // Extract the variant from the SysId + VariantSysId = SysId & ARM_FVP_SYS_ID_VARIANT_MASK; + + if (FvpSysId == ARM_FVP_BASE_BOARD_SYS_ID) { + if (VariantSysId == ARM_FVP_GIC_VE_MMAP) { + // FVP Base Model with legacy GIC memory map -- no longer supported + return ARM_FVP_BASE_AEMv8x4_AEMv8x4_GICV2_LEGACY; + } else { + GicRevision = ArmGicGetSupportedArchRevision (); + + if (GicRevision == ARM_GIC_ARCH_REVISION_2) { + // FVP Base Model with GICv2 support + return ARM_FVP_BASE_AEMv8x4_AEMv8x4_GICV2; + } else { + // FVP Base Model with GICv3 support + return ARM_FVP_BASE_AEMv8x4_AEMv8x4_GICV3; + } + } + } else if (FvpSysId == ARM_FVP_FOUNDATION_BOARD_SYS_ID) { + if (VariantSysId == ARM_FVP_GIC_VE_MMAP) { + // FVP Foundation Model with legacy GIC memory map -- no longer supported + return ARM_FVP_FOUNDATION_GICV2_LEGACY; + } else { + GicRevision = ArmGicGetSupportedArchRevision (); + + if (GicRevision == ARM_GIC_ARCH_REVISION_2) { + // FVP Foundation Model with GICv2 + return ARM_FVP_FOUNDATION_GICV2; + } else { + // FVP Foundation Model with GICv3 + return ARM_FVP_FOUNDATION_GICV3; + } + } + } + return ARM_FVP_UNKNOWN; +} + +/** + Return a pool allocated copy of the DTB image that is appropriate for + booting the current platform via DT. + + @param[out] Dtb Pointer to the DTB copy + @param[out] DtbSize Size of the DTB copy + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_NOT_FOUND No suitable DTB image could be located + @retval EFI_OUT_OF_RESOURCES No pool memory available + +**/ +EFI_STATUS +EFIAPI +DtPlatformLoadDtb ( + OUT VOID **Dtb, + OUT UINTN *DtbSize + ) +{ + EFI_STATUS Status; + VOID *OrigDtb; + VOID *CopyDtb; + UINTN OrigDtbSize; + ARM_VEXPRESS_PLATFORM_ID PlatformId; + + PlatformId = GetPlatformId (); + ASSERT (PlatformId < ARM_FVP_UNKNOWN); + if (PlatformId >= ARM_FVP_UNKNOWN) { + return EFI_NOT_FOUND; + } + + Status = GetSectionFromAnyFv (&gDtPlatformDefaultDtbFileGuid, + EFI_SECTION_RAW, (UINTN)PlatformId, &OrigDtb, &OrigDtbSize); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + CopyDtb = AllocateCopyPool (OrigDtbSize, OrigDtb); + if (CopyDtb == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + *Dtb = CopyDtb; + *DtbSize = OrigDtbSize; + + return EFI_SUCCESS; +} diff --git a/Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.inf b/Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.inf new file mode 100644 index 000000000000..5012101fe8db --- /dev/null +++ b/Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.inf @@ -0,0 +1,39 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = ArmVExpressDtPlatformDtbLoaderLib + FILE_GUID = 050d6041-1508-4ae7-a69f-250155ccb567 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = DtPlatformDtbLoaderLib|DXE_DRIVER + +[Sources] + ArmVExpressDtPlatformDtbLoaderLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + ArmGicLib + BaseLib + DxeServicesLib + IoLib + MemoryAllocationLib + +[Guids] + gDtPlatformDefaultDtbFileGuid -- 2.9.3 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 07/13] Platforms/FVP-AArch64: switch to simpler DT platform driver 2017-03-31 14:15 [PATCH v2 00/13] EDK2 spring cleaning -- OpenPlatformPkg edition Ard Biesheuvel ` (5 preceding siblings ...) 2017-03-31 14:15 ` [PATCH v2 06/13] Platforms/FVP: add DtPlatformDtbLoaderLib implementation Ard Biesheuvel @ 2017-03-31 14:15 ` Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 08/13] Platforms/Juno: add non-discoverable device driver and library Ard Biesheuvel ` (2 subsequent siblings) 9 siblings, 0 replies; 15+ messages in thread From: Ard Biesheuvel @ 2017-03-31 14:15 UTC (permalink / raw) To: edk2-devel, leif.lindholm, ryan.harkin; +Cc: Ard Biesheuvel Replace the elaborate but awkward FdtPlatformDxe with the new DtPlatformDxe, which supports embedded DTBs only. This is sufficient for virtually all use cases, and if it is not, there are various way to override the device tree binary presented to the OS. As a bonus, this driver makes ACPI and DT mutually exclusive - this can be configured via the setup screen. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 27 +++++++------- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf | 37 ++++++-------------- 2 files changed, 24 insertions(+), 40 deletions(-) diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc index e6778aafe8c6..1125f22f9172 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc @@ -35,6 +35,7 @@ DEFINE EDK2_SKIP_PEICORE=1 !endif + DT_SUPPORT = FALSE !include OpenPlatformPkg/Platforms/ARM/VExpress/ArmVExpress.dsc.inc @@ -59,6 +60,8 @@ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf !endif + DtPlatformDtbLoaderLib|OpenPlatformPkg/Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.inf + [LibraryClasses.common.SEC] ArmPlatformSecLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/ArmVExpressSecLib.inf ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf @@ -173,15 +176,6 @@ # the entire FVP address space can be covered by 36 bit VAs gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36 -[PcdsDynamicDefault.common] - # - # The size of a dynamic PCD of the (VOID*) type can not be increased at run - # time from its size at build time. Set the "PcdFdtDevicePaths" PCD to a 128 - # character "empty" string, to allow to be able to set FDT text device paths - # up to 128 characters long. - # - gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths|L" " - ################################################################################ # # Components Section - list of all EDK II Modules needed by this Platform @@ -262,7 +256,13 @@ # # ACPI Support # - MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { +!if $(DT_SUPPORT) == TRUE + <LibraryClasses> + NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf +!endif + } + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf OpenPlatformPkg/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf @@ -316,10 +316,9 @@ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf } +!if $(DT_SUPPORT) == TRUE # # FDT installation # - EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf { - <LibraryClasses> - BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf - } + EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf +!endif diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf index 262515150dd9..7b2397417534 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf @@ -170,35 +170,20 @@ FvNameGuid = 87940482-fc81-41c3-87e6-399cf85ac8a0 # FV Filesystem INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf +!if $(DT_SUPPORT) == TRUE # # FDT installation # - # The UEFI driver is at the end of the list of the driver to be dispatched - # after the device drivers (eg: Ethernet) to ensure we have support for them. - INF EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf - -!ifdef $(DTB_DIR) - # - # Embed flattened device tree (FDT) images for all known - # variants of this platform - # - FILE RAW = PCD (gArmVExpressTokenSpaceGuid.PcdFdtFvpBaseAEMv8x4GicV2) { - $(DTB_DIR)/fvp-base-gicv2-psci.dtb - } - FILE RAW = PCD (gArmVExpressTokenSpaceGuid.PcdFdtFvpBaseAEMv8x4GicV2Legacy) { - $(DTB_DIR)/fvp-base-gicv2legacy-psci.dtb - } - FILE RAW = PCD (gArmVExpressTokenSpaceGuid.PcdFdtFvpBaseAEMv8x4GicV3) { - $(DTB_DIR)/fvp-base-gicv3-psci.dtb - } - FILE RAW = PCD (gArmVExpressTokenSpaceGuid.PcdFdtFvpFoundationGicV2) { - $(DTB_DIR)/fvp-foundation-gicv2-psci.dtb - } - FILE RAW = PCD (gArmVExpressTokenSpaceGuid.PcdFdtFvpFoundationGicV2Legacy) { - $(DTB_DIR)/fvp-foundation-gicv2legacy-psci.dtb - } - FILE RAW = PCD (gArmVExpressTokenSpaceGuid.PcdFdtFvpFoundationGicV3) { - $(DTB_DIR)/fvp-foundation-gicv3-psci.dtb + INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf + + # builtin device tree binaries -- order matches ARM_VEXPRESS_PLATFORM_ID + FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { + SECTION RAW = OpenPlatformPkg/Platforms/ARM/VExpress/DeviceTree/fvp-base-gicv2-psci.dtb + SECTION RAW = OpenPlatformPkg/Platforms/ARM/VExpress/DeviceTree/fvp-base-gicv2legacy-psci.dtb + SECTION RAW = OpenPlatformPkg/Platforms/ARM/VExpress/DeviceTree/fvp-base-gicv3-psci.dtb + SECTION RAW = OpenPlatformPkg/Platforms/ARM/VExpress/DeviceTree/fvp-foundation-gicv2-psci.dtb + SECTION RAW = OpenPlatformPkg/Platforms/ARM/VExpress/DeviceTree/fvp-foundation-gicv2legacy-psci.dtb + SECTION RAW = OpenPlatformPkg/Platforms/ARM/VExpress/DeviceTree/fvp-foundation-gicv3-psci.dtb } !endif -- 2.9.3 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 08/13] Platforms/Juno: add non-discoverable device driver and library 2017-03-31 14:15 [PATCH v2 00/13] EDK2 spring cleaning -- OpenPlatformPkg edition Ard Biesheuvel ` (6 preceding siblings ...) 2017-03-31 14:15 ` [PATCH v2 07/13] Platforms/FVP-AArch64: switch to simpler DT platform driver Ard Biesheuvel @ 2017-03-31 14:15 ` Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 09/13] Platforms/Juno: add PciHostBridgeLib implementation Ard Biesheuvel 2017-03-31 14:19 ` [PATCH v2 10/13] Platforms/Juno: switch to generic PCI host bridge driver Ard Biesheuvel 9 siblings, 0 replies; 15+ messages in thread From: Ard Biesheuvel @ 2017-03-31 14:15 UTC (permalink / raw) To: edk2-devel, leif.lindholm, ryan.harkin; +Cc: Ard Biesheuvel In preparation of moving ArmJunoDxe's support of the OHCI and EHCI controllers to the generic non-discoverable device infrastructure, add the prerequisite driver and library class resolution to the Juno platform description. Note that the FD image size needs to be increased slightly to accommodate the added code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/ARM/Juno/ArmJuno.dsc | 2 ++ Platforms/ARM/Juno/ArmJuno.fdf | 7 ++++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 71dc5463a84f..141616e13234 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -65,6 +65,7 @@ [LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER] PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf [BuildOptions] *_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmJunoPkg/Include @@ -307,6 +308,7 @@ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf # # Juno platform driver diff --git a/Platforms/ARM/Juno/ArmJuno.fdf b/Platforms/ARM/Juno/ArmJuno.fdf index aadde45164a5..3f96266fb625 100644 --- a/Platforms/ARM/Juno/ArmJuno.fdf +++ b/Platforms/ARM/Juno/ArmJuno.fdf @@ -26,12 +26,12 @@ [FD.BL33_AP_UEFI] BaseAddress = 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. -Size = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +Size = 0x000F8000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device ErasePolarity = 1 # This one is tricky, it must be: BlockSize * NumBlocks = Size BlockSize = 0x00001000 -NumBlocks = 0xF0 +NumBlocks = 0xF8 ################################################################################ # @@ -49,7 +49,7 @@ NumBlocks = 0xF0 # ################################################################################ -0x00000000|0x000F0000 +0x00000000|0x000F8000 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize FV = FVMAIN_COMPACT @@ -155,6 +155,7 @@ FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270092 INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf # # PCI Support -- 2.9.3 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 09/13] Platforms/Juno: add PciHostBridgeLib implementation 2017-03-31 14:15 [PATCH v2 00/13] EDK2 spring cleaning -- OpenPlatformPkg edition Ard Biesheuvel ` (7 preceding siblings ...) 2017-03-31 14:15 ` [PATCH v2 08/13] Platforms/Juno: add non-discoverable device driver and library Ard Biesheuvel @ 2017-03-31 14:15 ` Ard Biesheuvel 2017-04-04 8:31 ` Ard Biesheuvel 2017-03-31 14:19 ` [PATCH v2 10/13] Platforms/Juno: switch to generic PCI host bridge driver Ard Biesheuvel 9 siblings, 1 reply; 15+ messages in thread From: Ard Biesheuvel @ 2017-03-31 14:15 UTC (permalink / raw) To: edk2-devel, leif.lindholm, ryan.harkin; +Cc: Ard Biesheuvel In order to be able to switch to the generic PCI host bridge driver, implement the glue library that exposes the PCIe parameters to the common driver. Since the Juno performs some initialization of the PCIe control registers as well, copy that code into the library's constructor. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c | 185 +++++++++++++++++++ Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf | 77 ++++++++ Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.c | 191 ++++++++++++++++++++ Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.h | 107 +++++++++++ 4 files changed, 560 insertions(+) diff --git a/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c new file mode 100644 index 000000000000..213b5ef64e6d --- /dev/null +++ b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c @@ -0,0 +1,185 @@ +/** @file + PCI Host Bridge Library instance for ARM Juno + + Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR> + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include <PiDxe.h> +#include <Library/PciHostBridgeLib.h> +#include <Library/DebugLib.h> +#include <Library/DevicePathLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PcdLib.h> + +#include <Protocol/PciRootBridgeIo.h> +#include <Protocol/PciHostBridgeResourceAllocation.h> + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A03), // PCI + 0 + }, { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } +}; + +STATIC PCI_ROOT_BRIDGE mRootBridge = { + 0, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + FixedPcdGet32 (PcdPciBusMin), + FixedPcdGet32 (PcdPciBusMax) + }, { + // Io + FixedPcdGet64 (PcdPciIoBase), + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 + }, { + // Mem + FixedPcdGet32 (PcdPciMmio32Base), + FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1 + }, { + // MemAbove4G + FixedPcdGet64 (PcdPciMmio64Base), + FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1 + }, { + // PMem + MAX_UINT64, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath +}; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + *Count = 1; + + return &mRootBridge; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ +} + + +STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = { + L"Mem", L"I/O", L"Bus" +}; + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the resources + for all the root bridges. The resource for each root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + .SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex; + DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n")); + + RootBridgeIndex = 0; + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { + ASSERT (Descriptor->ResType < + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr) + ); + DEBUG ((EFI_D_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((EFI_D_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE + ) != 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} diff --git a/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf new file mode 100644 index 000000000000..ef502937f6c2 --- /dev/null +++ b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf @@ -0,0 +1,77 @@ +## @file +# PCI Host Bridge Library instance for ARM Juno +# +# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made available +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AmdStyxPciHostBridgeLib + FILE_GUID = d92c722c-87f9-4988-843e-dffd6bc8c5e3 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER + CONSTRUCTOR = HWPciRbInit + +# +# The following information is for reference only and not required by the build +# tools. +# +# VALID_ARCHITECTURES = AARCH64 ARM +# + +[Sources] + JunoPciHostBridgeLib.c + XPressRich3.c + +[Packages] + ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + DebugLib + DevicePathLib + IoLib + MemoryAllocationLib + UefiBootServicesTableLib + +[Pcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + +[FixedPcd] + gArmTokenSpaceGuid.PcdPciBusMin + gArmTokenSpaceGuid.PcdPciBusMax + gArmTokenSpaceGuid.PcdPciIoBase + gArmTokenSpaceGuid.PcdPciIoSize + gArmTokenSpaceGuid.PcdPciIoTranslation + gArmTokenSpaceGuid.PcdPciMmio32Base + gArmTokenSpaceGuid.PcdPciMmio32Size + gArmTokenSpaceGuid.PcdPciMmio32Translation + gArmTokenSpaceGuid.PcdPciMmio64Base + gArmTokenSpaceGuid.PcdPciMmio64Size + gArmTokenSpaceGuid.PcdPciMmio64Translation + + gArmJunoTokenSpaceGuid.PcdPcieControlBaseAddress + gArmJunoTokenSpaceGuid.PcdPcieRootPortBaseAddress + gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress + gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize + +[Protocols] + gEfiCpuIo2ProtocolGuid ## CONSUMES + +[Depex] + gEfiCpuIo2ProtocolGuid diff --git a/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.c b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.c new file mode 100644 index 000000000000..edfad300553e --- /dev/null +++ b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.c @@ -0,0 +1,191 @@ +/** @file +* Initialize the XPress-RICH3 PCIe Root complex +* +* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <PiDxe.h> + +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <IndustryStandard/Pci22.h> + +#include "XPressRich3.h" +#include "ArmPlatform.h" + +#define PCI_BRIDGE_REVISION_ID 1 +#define CLASS_CODE_REGISTER(Class, SubClass, ProgIf) ((Class << 16) | (SubClass << 8) | ProgIf) +#define PLDA_BRIDGE_CCR CLASS_CODE_REGISTER(PCI_CLASS_BRIDGE, \ + PCI_CLASS_BRIDGE_P2P, \ + PCI_IF_BRIDGE_P2P) + +STATIC +VOID +SetTranslationAddressEntry ( + IN EFI_CPU_IO2_PROTOCOL *CpuIo, + IN UINTN Entry, + IN UINT64 SourceAddress, + IN UINT64 TranslatedAddress, + IN UINT64 TranslationSize, + IN UINT64 TranslationParameter + ) +{ + UINTN Log2Size = HighBitSet64 (TranslationSize); + + // Ensure the size is a power of two. Restriction form the AXI Translation logic + // Othwerwise we increase the translation size + if (TranslationSize != (1ULL << Log2Size)) { + DEBUG ((EFI_D_WARN, "PCI: The size 0x%lX of the region 0x%lx has been increased to " + "be a power of two for the AXI translation table.\n", + TranslationSize, SourceAddress)); + Log2Size++; + } + + PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_SRC_ADDR_LOW_SIZE, + (UINT32)SourceAddress | ((Log2Size - 1) << 1) | 0x1); + PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_SRC_ADDR_HI, SourceAddress >> 32); + + PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_ADDR_LOW, (UINT32)TranslatedAddress); + PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_ADDR_HI, TranslatedAddress >> 32); + + PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_PARAM, TranslationParameter); +} + +EFI_STATUS +HWPciRbInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT32 Value; + UINT32 Index; + UINTN TranslationTable; + EFI_CPU_IO2_PROTOCOL *CpuIo; + EFI_STATUS Status; + UINT32 JunoRevision; + + PCI_TRACE ("VExpressPciRbInit()"); + + // + // Juno R0 has no working PCIe + // + GetJunoRevision (JunoRevision); + if (JunoRevision < JUNO_REVISION_R1) { + return EFI_NOT_FOUND; + } + + PCI_TRACE ("PCIe Setting up Address Translation"); + + Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, + (VOID **)&CpuIo); + ASSERT_EFI_ERROR (Status); + + // The Juno PIO window is 8M, so we need full 32-bit PIO decoding. + PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_IO32 | + PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); + + // Setup the PCI Configuration Registers + // Offset 0a: SubClass 04 PCI-PCI Bridge + // Offset 0b: BaseClass 06 Bridge Device + // The Class Code register is a 24 bit and can be configured by setting up the PCIE_PCI_IDS + // Refer [1] Chapter 13 + PCIE_ROOTPORT_WRITE32 (PCIE_PCI_IDS + PCIE_PCI_IDS_CLASSCODE_OFFSET, ((PLDA_BRIDGE_CCR << 8) | PCI_BRIDGE_REVISION_ID)); + + // + // PCIE Window 0 -> AXI4 Master 0 Address Translations + // + TranslationTable = VEXPRESS_ATR_PCIE_WIN0; + + // MSI Support + SetTranslationAddressEntry (CpuIo, TranslationTable, ARM_JUNO_GIV2M_MSI_BASE, ARM_JUNO_GIV2M_MSI_BASE, + ARM_JUNO_GIV2M_MSI_SZ, PCI_ATR_TRSLID_AXIDEVICE); + TranslationTable += PCI_ATR_ENTRY_SIZE; + + // System Memory Support + SetTranslationAddressEntry (CpuIo, TranslationTable, PcdGet64 (PcdSystemMemoryBase), PcdGet64 (PcdSystemMemoryBase), + PcdGet64 (PcdSystemMemorySize), PCI_ATR_TRSLID_AXIMEMORY); + TranslationTable += PCI_ATR_ENTRY_SIZE; + SetTranslationAddressEntry (CpuIo, TranslationTable, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE, + ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ, PCI_ATR_TRSLID_AXIMEMORY); + + // + // AXI4 Slave 1 -> PCIE Window 0 Address Translations + // + TranslationTable = VEXPRESS_ATR_AXI4_SLV1; + + // PCI ECAM Support + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF); + TranslationTable += PCI_ATR_ENTRY_SIZE; + + // PCI IO Support, the PIO space is translated from the arm MMIO PCI_IO_BASE address to the PIO base address of 0 + // AKA, PIO addresses used by endpoints are generally in the range of 0-64K. + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, 0, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); + TranslationTable += PCI_ATR_ENTRY_SIZE; + + // PCI MEM32 Support + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_MEM32_BASE, PCI_MEM32_BASE, PCI_MEM32_SIZE, PCI_ATR_TRSLID_PCIE_MEMORY); + TranslationTable += PCI_ATR_ENTRY_SIZE; + + // PCI MEM64 Support + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_MEM64_BASE, PCI_MEM64_BASE, PCI_MEM64_SIZE, PCI_ATR_TRSLID_PCIE_MEMORY); + + // Add credits + PCIE_ROOTPORT_WRITE32 (PCIE_VC_CRED, 0x00f0b818); + PCIE_ROOTPORT_WRITE32 (PCIE_VC_CRED + 4, 0x1); + + // Allow ECRC + PCIE_ROOTPORT_WRITE32 (PCIE_PEX_SPC2, 0x6006); + + // Reset controller + PCIE_CONTROL_WRITE32 (PCIE_CONTROL_RST_CTL, PCIE_CONTROL_RST_CTL_RCPHY_REL); + + // Wait for reset + for (Index = 0; Index < 1000; Index++) { + gBS->Stall (1000); + PCIE_CONTROL_READ32 (PCIE_CONTROL_RST_STS, Value); + if ((Value & PCIE_CONTROL_RST_STS_RCPHYPLL_OUT) == PCIE_CONTROL_RST_STS_RCPHYPLL_OUT) { + break; + } + } + + // Check for reset + if (!(Value & PCIE_CONTROL_RST_STS_RCPHYPLL_OUT)) { + DEBUG ((EFI_D_ERROR, "PCIe failed to come out of reset: %x.\n", Value)); + return EFI_NOT_READY; + } + + gBS->Stall (1000); + PCI_TRACE ("Checking link Status..."); + + // Wait for Link Up + for (Index = 0; Index < 1000; Index++) { + gBS->Stall (1000); + PCIE_ROOTPORT_READ32 (VEXPRESS_BASIC_STATUS, Value); + if (Value & LINK_UP) { + break; + } + } + + // Check for link up + if (!(Value & LINK_UP)) { + DEBUG ((EFI_D_ERROR, "PCIe link not up: %x.\n", Value)); + return EFI_NOT_READY; + } + + PCIE_ROOTPORT_WRITE32 (PCIE_IMASK_LOCAL, PCIE_INT_MSI | PCIE_INT_INTx); + + return EFI_SUCCESS; +} diff --git a/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.h b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.h new file mode 100644 index 000000000000..07f52c210ed9 --- /dev/null +++ b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.h @@ -0,0 +1,107 @@ +/** @file +* Header containing the Xpress-RICH3 PCIe Root Complex specific values +* +* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __XPRESS_RICH3_H__ +#define __XPRESS_RICH3_H__ + +#include <Protocol/CpuIo2.h> +#include <Library/PcdLib.h> + +#define PCI_ECAM_BASE FixedPcdGet64 (PcdPciConfigurationSpaceBaseAddress) +#define PCI_ECAM_SIZE FixedPcdGet64 (PcdPciConfigurationSpaceSize) +#define PCI_IO_BASE FixedPcdGet64 (PcdPciIoTranslation) +#define PCI_IO_SIZE FixedPcdGet64 (PcdPciIoSize) +#define PCI_MEM32_BASE FixedPcdGet64 (PcdPciMmio32Base) +#define PCI_MEM32_SIZE FixedPcdGet64 (PcdPciMmio32Size) +#define PCI_MEM64_BASE FixedPcdGet64 (PcdPciMmio64Base) +#define PCI_MEM64_SIZE FixedPcdGet64 (PcdPciMmio64Size) + +#define PCI_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_PCI: " txt "\n")) + +#define PCIE_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Value); } +#define PCIE_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Val); } + +#define PCIE_CONTROL_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Value); } +#define PCIE_CONTROL_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Val); } + +/* + * Bridge Internal Registers + */ + +// PCIe Available Credit Settings +#define PCIE_VC_CRED 0x090 +// PCIe PCI Standard Configuration Identification Settings registers +#define PCIE_PCI_IDS 0x098 +#define PCIE_PCI_IDS_CLASSCODE_OFFSET 0x4 +// PCIe Specific 2 Capabilities Settings +#define PCIE_PEX_SPC2 0x0d8 +// PCIe Windows Settings register +#define PCIE_BAR_WIN 0x0FC +// Local Processor Interrupt Mask +#define PCIE_IMASK_LOCAL 0x180 + +#define PCIE_BAR_WIN_SUPPORT_IO BIT0 +#define PCIE_BAR_WIN_SUPPORT_IO32 BIT1 +#define PCIE_BAR_WIN_SUPPORT_MEM BIT2 +#define PCIE_BAR_WIN_SUPPORT_MEM64 BIT3 + +#define PCIE_INT_MSI BIT28 +#define PCIE_INT_A BIT24 +#define PCIE_INT_B BIT25 +#define PCIE_INT_C BIT26 +#define PCIE_INT_D BIT27 +#define PCIE_INT_INTx (PCIE_INT_A | PCIE_INT_B |\ + PCIE_INT_C | PCIE_INT_D) + +/* + * PCIe Control Registers + */ +#define PCIE_CONTROL_RST_CTL 0x1004 +#define PCIE_CONTROL_RST_STS 0x1008 + +/* + * PCI Express Address Translation registers + * All are offsets from PcdPcieControlBaseAddress + */ +#define VEXPRESS_ATR_PCIE_WIN0 0x600 +#define VEXPRESS_ATR_AXI4_SLV0 0x800 +#define VEXPRESS_ATR_AXI4_SLV1 0x820 + +#define PCI_ATR_ENTRY_SIZE 0x20 +#define PCI_ATR_SRC_ADDR_LOW_SIZE 0 +#define PCI_ATR_SRC_ADDR_HI 0x4 +#define PCI_ATR_TRSL_ADDR_LOW 0x8 +#define PCI_ATR_TRSL_ADDR_HI 0xc +#define PCI_ATR_TRSL_PARAM 0x10 + +#define PCI_ATR_TRSLID_AXIDEVICE 0x420004 +#define PCI_ATR_TRSLID_AXIMEMORY 0x4e0004 +#define PCI_ATR_TRSLID_PCIE_CONF 0x000001 +#define PCI_ATR_TRSLID_PCIE_IO 0x020000 +#define PCI_ATR_TRSLID_PCIE_MEMORY 0x000000 + +#define PCIE_CONTROL_RST_CTL_RC_REL (1 << 1) +#define PCIE_CONTROL_RST_CTL_PHY_REL (1 << 0) +#define PCIE_CONTROL_RST_CTL_RCPHY_REL (PCIE_CONTROL_RST_CTL_RC_REL | PCIE_CONTROL_RST_CTL_PHY_REL) + +#define PCIE_CONTROL_RST_STS_RC_ST (1 << 2) +#define PCIE_CONTROL_RST_STS_PHY_ST (1 << 1) +#define PCIE_CONTROL_RST_STS_PLL_ST (1 << 0) +#define PCIE_CONTROL_RST_STS_RCPHYPLL_OUT (PCIE_CONTROL_RST_STS_RC_ST | PCIE_CONTROL_RST_STS_PHY_ST | PCIE_CONTROL_RST_STS_PLL_ST) + +#define VEXPRESS_BASIC_STATUS 0x18 +#define LINK_UP 0xff + +#endif -- 2.9.3 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2 09/13] Platforms/Juno: add PciHostBridgeLib implementation 2017-03-31 14:15 ` [PATCH v2 09/13] Platforms/Juno: add PciHostBridgeLib implementation Ard Biesheuvel @ 2017-04-04 8:31 ` Ard Biesheuvel 0 siblings, 0 replies; 15+ messages in thread From: Ard Biesheuvel @ 2017-04-04 8:31 UTC (permalink / raw) To: edk2-devel@lists.01.org, Leif Lindholm, Ryan Harkin; +Cc: Ard Biesheuvel On 31 March 2017 at 15:15, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote: > In order to be able to switch to the generic PCI host bridge driver, > implement the glue library that exposes the PCIe parameters to the > common driver. Since the Juno performs some initialization of the > PCIe control registers as well, copy that code into the library's > constructor. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> One copy-paste error below (in the BASE_NAME) but this does not affect functionality. Will fix that up for v3. > --- > Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c | 185 +++++++++++++++++++ > Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf | 77 ++++++++ > Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.c | 191 ++++++++++++++++++++ > Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.h | 107 +++++++++++ > 4 files changed, 560 insertions(+) > > diff --git a/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c > new file mode 100644 > index 000000000000..213b5ef64e6d > --- /dev/null > +++ b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c > @@ -0,0 +1,185 @@ > +/** @file > + PCI Host Bridge Library instance for ARM Juno > + > + Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR> > + > + This program and the accompanying materials are licensed and made available > + under the terms and conditions of the BSD License which accompanies this > + distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php. > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT > + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > +#include <PiDxe.h> > +#include <Library/PciHostBridgeLib.h> > +#include <Library/DebugLib.h> > +#include <Library/DevicePathLib.h> > +#include <Library/MemoryAllocationLib.h> > +#include <Library/PcdLib.h> > + > +#include <Protocol/PciRootBridgeIo.h> > +#include <Protocol/PciHostBridgeResourceAllocation.h> > + > +#pragma pack(1) > +typedef struct { > + ACPI_HID_DEVICE_PATH AcpiDevicePath; > + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; > +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; > +#pragma pack () > + > +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), > + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) > + } > + }, > + EISA_PNP_ID(0x0A03), // PCI > + 0 > + }, { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > +}; > + > +STATIC PCI_ROOT_BRIDGE mRootBridge = { > + 0, // Segment > + 0, // Supports > + 0, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, > + { > + // Bus > + FixedPcdGet32 (PcdPciBusMin), > + FixedPcdGet32 (PcdPciBusMax) > + }, { > + // Io > + FixedPcdGet64 (PcdPciIoBase), > + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 > + }, { > + // Mem > + FixedPcdGet32 (PcdPciMmio32Base), > + FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1 > + }, { > + // MemAbove4G > + FixedPcdGet64 (PcdPciMmio64Base), > + FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1 > + }, { > + // PMem > + MAX_UINT64, > + 0 > + }, { > + // PMemAbove4G > + MAX_UINT64, > + 0 > + }, > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath > +}; > + > +/** > + Return all the root bridge instances in an array. > + > + @param Count Return the count of root bridge instances. > + > + @return All the root bridge instances in an array. > + The array should be passed into PciHostBridgeFreeRootBridges() > + when it's not used. > +**/ > +PCI_ROOT_BRIDGE * > +EFIAPI > +PciHostBridgeGetRootBridges ( > + UINTN *Count > + ) > +{ > + *Count = 1; > + > + return &mRootBridge; > +} > + > +/** > + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). > + > + @param Bridges The root bridge instances array. > + @param Count The count of the array. > +**/ > +VOID > +EFIAPI > +PciHostBridgeFreeRootBridges ( > + PCI_ROOT_BRIDGE *Bridges, > + UINTN Count > + ) > +{ > +} > + > + > +STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = { > + L"Mem", L"I/O", L"Bus" > +}; > + > +/** > + Inform the platform that the resource conflict happens. > + > + @param HostBridgeHandle Handle of the Host Bridge. > + @param Configuration Pointer to PCI I/O and PCI memory resource > + descriptors. The Configuration contains the resources > + for all the root bridges. The resource for each root > + bridge is terminated with END descriptor and an > + additional END is appended indicating the end of the > + entire resources. The resource descriptor field > + values follow the description in > + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL > + .SubmitResources(). > +**/ > +VOID > +EFIAPI > +PciHostBridgeResourceConflict ( > + EFI_HANDLE HostBridgeHandle, > + VOID *Configuration > + ) > +{ > + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; > + UINTN RootBridgeIndex; > + DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n")); > + > + RootBridgeIndex = 0; > + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; > + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { > + DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); > + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { > + ASSERT (Descriptor->ResType < > + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr) > + ); > + DEBUG ((EFI_D_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", > + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], > + Descriptor->AddrLen, Descriptor->AddrRangeMax > + )); > + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { > + DEBUG ((EFI_D_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", > + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, > + ((Descriptor->SpecificFlag & > + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE > + ) != 0) ? L" (Prefetchable)" : L"" > + )); > + } > + } > + // > + // Skip the END descriptor for root bridge > + // > + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); > + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( > + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 > + ); > + } > +} > diff --git a/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf > new file mode 100644 > index 000000000000..ef502937f6c2 > --- /dev/null > +++ b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf > @@ -0,0 +1,77 @@ > +## @file > +# PCI Host Bridge Library instance for ARM Juno > +# > +# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR> > +# > +# This program and the accompanying materials are licensed and made available > +# under the terms and conditions of the BSD License which accompanies this > +# distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > +# IMPLIED. > +# > +# > +## > + > +[Defines] > + INF_VERSION = 0x00010005 > + BASE_NAME = AmdStyxPciHostBridgeLib > + FILE_GUID = d92c722c-87f9-4988-843e-dffd6bc8c5e3 > + MODULE_TYPE = DXE_DRIVER > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER > + CONSTRUCTOR = HWPciRbInit > + > +# > +# The following information is for reference only and not required by the build > +# tools. > +# > +# VALID_ARCHITECTURES = AARCH64 ARM > +# > + > +[Sources] > + JunoPciHostBridgeLib.c > + XPressRich3.c > + > +[Packages] > + ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec > + ArmPkg/ArmPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + > +[LibraryClasses] > + BaseLib > + DebugLib > + DevicePathLib > + IoLib > + MemoryAllocationLib > + UefiBootServicesTableLib > + > +[Pcd] > + gArmTokenSpaceGuid.PcdSystemMemoryBase > + gArmTokenSpaceGuid.PcdSystemMemorySize > + > +[FixedPcd] > + gArmTokenSpaceGuid.PcdPciBusMin > + gArmTokenSpaceGuid.PcdPciBusMax > + gArmTokenSpaceGuid.PcdPciIoBase > + gArmTokenSpaceGuid.PcdPciIoSize > + gArmTokenSpaceGuid.PcdPciIoTranslation > + gArmTokenSpaceGuid.PcdPciMmio32Base > + gArmTokenSpaceGuid.PcdPciMmio32Size > + gArmTokenSpaceGuid.PcdPciMmio32Translation > + gArmTokenSpaceGuid.PcdPciMmio64Base > + gArmTokenSpaceGuid.PcdPciMmio64Size > + gArmTokenSpaceGuid.PcdPciMmio64Translation > + > + gArmJunoTokenSpaceGuid.PcdPcieControlBaseAddress > + gArmJunoTokenSpaceGuid.PcdPcieRootPortBaseAddress > + gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress > + gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize > + > +[Protocols] > + gEfiCpuIo2ProtocolGuid ## CONSUMES > + > +[Depex] > + gEfiCpuIo2ProtocolGuid > diff --git a/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.c b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.c > new file mode 100644 > index 000000000000..edfad300553e > --- /dev/null > +++ b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.c > @@ -0,0 +1,191 @@ > +/** @file > +* Initialize the XPress-RICH3 PCIe Root complex > +* > +* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. > +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include <PiDxe.h> > + > +#include <Library/BaseLib.h> > +#include <Library/DebugLib.h> > +#include <Library/IoLib.h> > +#include <Library/UefiBootServicesTableLib.h> > + > +#include <IndustryStandard/Pci22.h> > + > +#include "XPressRich3.h" > +#include "ArmPlatform.h" > + > +#define PCI_BRIDGE_REVISION_ID 1 > +#define CLASS_CODE_REGISTER(Class, SubClass, ProgIf) ((Class << 16) | (SubClass << 8) | ProgIf) > +#define PLDA_BRIDGE_CCR CLASS_CODE_REGISTER(PCI_CLASS_BRIDGE, \ > + PCI_CLASS_BRIDGE_P2P, \ > + PCI_IF_BRIDGE_P2P) > + > +STATIC > +VOID > +SetTranslationAddressEntry ( > + IN EFI_CPU_IO2_PROTOCOL *CpuIo, > + IN UINTN Entry, > + IN UINT64 SourceAddress, > + IN UINT64 TranslatedAddress, > + IN UINT64 TranslationSize, > + IN UINT64 TranslationParameter > + ) > +{ > + UINTN Log2Size = HighBitSet64 (TranslationSize); > + > + // Ensure the size is a power of two. Restriction form the AXI Translation logic > + // Othwerwise we increase the translation size > + if (TranslationSize != (1ULL << Log2Size)) { > + DEBUG ((EFI_D_WARN, "PCI: The size 0x%lX of the region 0x%lx has been increased to " > + "be a power of two for the AXI translation table.\n", > + TranslationSize, SourceAddress)); > + Log2Size++; > + } > + > + PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_SRC_ADDR_LOW_SIZE, > + (UINT32)SourceAddress | ((Log2Size - 1) << 1) | 0x1); > + PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_SRC_ADDR_HI, SourceAddress >> 32); > + > + PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_ADDR_LOW, (UINT32)TranslatedAddress); > + PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_ADDR_HI, TranslatedAddress >> 32); > + > + PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_PARAM, TranslationParameter); > +} > + > +EFI_STATUS > +HWPciRbInit ( > + IN EFI_HANDLE ImageHandle, > + IN EFI_SYSTEM_TABLE *SystemTable > + ) > +{ > + UINT32 Value; > + UINT32 Index; > + UINTN TranslationTable; > + EFI_CPU_IO2_PROTOCOL *CpuIo; > + EFI_STATUS Status; > + UINT32 JunoRevision; > + > + PCI_TRACE ("VExpressPciRbInit()"); > + > + // > + // Juno R0 has no working PCIe > + // > + GetJunoRevision (JunoRevision); > + if (JunoRevision < JUNO_REVISION_R1) { > + return EFI_NOT_FOUND; > + } > + > + PCI_TRACE ("PCIe Setting up Address Translation"); > + > + Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, > + (VOID **)&CpuIo); > + ASSERT_EFI_ERROR (Status); > + > + // The Juno PIO window is 8M, so we need full 32-bit PIO decoding. > + PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_IO32 | > + PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); > + > + // Setup the PCI Configuration Registers > + // Offset 0a: SubClass 04 PCI-PCI Bridge > + // Offset 0b: BaseClass 06 Bridge Device > + // The Class Code register is a 24 bit and can be configured by setting up the PCIE_PCI_IDS > + // Refer [1] Chapter 13 > + PCIE_ROOTPORT_WRITE32 (PCIE_PCI_IDS + PCIE_PCI_IDS_CLASSCODE_OFFSET, ((PLDA_BRIDGE_CCR << 8) | PCI_BRIDGE_REVISION_ID)); > + > + // > + // PCIE Window 0 -> AXI4 Master 0 Address Translations > + // > + TranslationTable = VEXPRESS_ATR_PCIE_WIN0; > + > + // MSI Support > + SetTranslationAddressEntry (CpuIo, TranslationTable, ARM_JUNO_GIV2M_MSI_BASE, ARM_JUNO_GIV2M_MSI_BASE, > + ARM_JUNO_GIV2M_MSI_SZ, PCI_ATR_TRSLID_AXIDEVICE); > + TranslationTable += PCI_ATR_ENTRY_SIZE; > + > + // System Memory Support > + SetTranslationAddressEntry (CpuIo, TranslationTable, PcdGet64 (PcdSystemMemoryBase), PcdGet64 (PcdSystemMemoryBase), > + PcdGet64 (PcdSystemMemorySize), PCI_ATR_TRSLID_AXIMEMORY); > + TranslationTable += PCI_ATR_ENTRY_SIZE; > + SetTranslationAddressEntry (CpuIo, TranslationTable, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE, > + ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ, PCI_ATR_TRSLID_AXIMEMORY); > + > + // > + // AXI4 Slave 1 -> PCIE Window 0 Address Translations > + // > + TranslationTable = VEXPRESS_ATR_AXI4_SLV1; > + > + // PCI ECAM Support > + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF); > + TranslationTable += PCI_ATR_ENTRY_SIZE; > + > + // PCI IO Support, the PIO space is translated from the arm MMIO PCI_IO_BASE address to the PIO base address of 0 > + // AKA, PIO addresses used by endpoints are generally in the range of 0-64K. > + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, 0, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); > + TranslationTable += PCI_ATR_ENTRY_SIZE; > + > + // PCI MEM32 Support > + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_MEM32_BASE, PCI_MEM32_BASE, PCI_MEM32_SIZE, PCI_ATR_TRSLID_PCIE_MEMORY); > + TranslationTable += PCI_ATR_ENTRY_SIZE; > + > + // PCI MEM64 Support > + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_MEM64_BASE, PCI_MEM64_BASE, PCI_MEM64_SIZE, PCI_ATR_TRSLID_PCIE_MEMORY); > + > + // Add credits > + PCIE_ROOTPORT_WRITE32 (PCIE_VC_CRED, 0x00f0b818); > + PCIE_ROOTPORT_WRITE32 (PCIE_VC_CRED + 4, 0x1); > + > + // Allow ECRC > + PCIE_ROOTPORT_WRITE32 (PCIE_PEX_SPC2, 0x6006); > + > + // Reset controller > + PCIE_CONTROL_WRITE32 (PCIE_CONTROL_RST_CTL, PCIE_CONTROL_RST_CTL_RCPHY_REL); > + > + // Wait for reset > + for (Index = 0; Index < 1000; Index++) { > + gBS->Stall (1000); > + PCIE_CONTROL_READ32 (PCIE_CONTROL_RST_STS, Value); > + if ((Value & PCIE_CONTROL_RST_STS_RCPHYPLL_OUT) == PCIE_CONTROL_RST_STS_RCPHYPLL_OUT) { > + break; > + } > + } > + > + // Check for reset > + if (!(Value & PCIE_CONTROL_RST_STS_RCPHYPLL_OUT)) { > + DEBUG ((EFI_D_ERROR, "PCIe failed to come out of reset: %x.\n", Value)); > + return EFI_NOT_READY; > + } > + > + gBS->Stall (1000); > + PCI_TRACE ("Checking link Status..."); > + > + // Wait for Link Up > + for (Index = 0; Index < 1000; Index++) { > + gBS->Stall (1000); > + PCIE_ROOTPORT_READ32 (VEXPRESS_BASIC_STATUS, Value); > + if (Value & LINK_UP) { > + break; > + } > + } > + > + // Check for link up > + if (!(Value & LINK_UP)) { > + DEBUG ((EFI_D_ERROR, "PCIe link not up: %x.\n", Value)); > + return EFI_NOT_READY; > + } > + > + PCIE_ROOTPORT_WRITE32 (PCIE_IMASK_LOCAL, PCIE_INT_MSI | PCIE_INT_INTx); > + > + return EFI_SUCCESS; > +} > diff --git a/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.h b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.h > new file mode 100644 > index 000000000000..07f52c210ed9 > --- /dev/null > +++ b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.h > @@ -0,0 +1,107 @@ > +/** @file > +* Header containing the Xpress-RICH3 PCIe Root Complex specific values > +* > +* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#ifndef __XPRESS_RICH3_H__ > +#define __XPRESS_RICH3_H__ > + > +#include <Protocol/CpuIo2.h> > +#include <Library/PcdLib.h> > + > +#define PCI_ECAM_BASE FixedPcdGet64 (PcdPciConfigurationSpaceBaseAddress) > +#define PCI_ECAM_SIZE FixedPcdGet64 (PcdPciConfigurationSpaceSize) > +#define PCI_IO_BASE FixedPcdGet64 (PcdPciIoTranslation) > +#define PCI_IO_SIZE FixedPcdGet64 (PcdPciIoSize) > +#define PCI_MEM32_BASE FixedPcdGet64 (PcdPciMmio32Base) > +#define PCI_MEM32_SIZE FixedPcdGet64 (PcdPciMmio32Size) > +#define PCI_MEM64_BASE FixedPcdGet64 (PcdPciMmio64Base) > +#define PCI_MEM64_SIZE FixedPcdGet64 (PcdPciMmio64Size) > + > +#define PCI_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_PCI: " txt "\n")) > + > +#define PCIE_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Value); } > +#define PCIE_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Val); } > + > +#define PCIE_CONTROL_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Value); } > +#define PCIE_CONTROL_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Val); } > + > +/* > + * Bridge Internal Registers > + */ > + > +// PCIe Available Credit Settings > +#define PCIE_VC_CRED 0x090 > +// PCIe PCI Standard Configuration Identification Settings registers > +#define PCIE_PCI_IDS 0x098 > +#define PCIE_PCI_IDS_CLASSCODE_OFFSET 0x4 > +// PCIe Specific 2 Capabilities Settings > +#define PCIE_PEX_SPC2 0x0d8 > +// PCIe Windows Settings register > +#define PCIE_BAR_WIN 0x0FC > +// Local Processor Interrupt Mask > +#define PCIE_IMASK_LOCAL 0x180 > + > +#define PCIE_BAR_WIN_SUPPORT_IO BIT0 > +#define PCIE_BAR_WIN_SUPPORT_IO32 BIT1 > +#define PCIE_BAR_WIN_SUPPORT_MEM BIT2 > +#define PCIE_BAR_WIN_SUPPORT_MEM64 BIT3 > + > +#define PCIE_INT_MSI BIT28 > +#define PCIE_INT_A BIT24 > +#define PCIE_INT_B BIT25 > +#define PCIE_INT_C BIT26 > +#define PCIE_INT_D BIT27 > +#define PCIE_INT_INTx (PCIE_INT_A | PCIE_INT_B |\ > + PCIE_INT_C | PCIE_INT_D) > + > +/* > + * PCIe Control Registers > + */ > +#define PCIE_CONTROL_RST_CTL 0x1004 > +#define PCIE_CONTROL_RST_STS 0x1008 > + > +/* > + * PCI Express Address Translation registers > + * All are offsets from PcdPcieControlBaseAddress > + */ > +#define VEXPRESS_ATR_PCIE_WIN0 0x600 > +#define VEXPRESS_ATR_AXI4_SLV0 0x800 > +#define VEXPRESS_ATR_AXI4_SLV1 0x820 > + > +#define PCI_ATR_ENTRY_SIZE 0x20 > +#define PCI_ATR_SRC_ADDR_LOW_SIZE 0 > +#define PCI_ATR_SRC_ADDR_HI 0x4 > +#define PCI_ATR_TRSL_ADDR_LOW 0x8 > +#define PCI_ATR_TRSL_ADDR_HI 0xc > +#define PCI_ATR_TRSL_PARAM 0x10 > + > +#define PCI_ATR_TRSLID_AXIDEVICE 0x420004 > +#define PCI_ATR_TRSLID_AXIMEMORY 0x4e0004 > +#define PCI_ATR_TRSLID_PCIE_CONF 0x000001 > +#define PCI_ATR_TRSLID_PCIE_IO 0x020000 > +#define PCI_ATR_TRSLID_PCIE_MEMORY 0x000000 > + > +#define PCIE_CONTROL_RST_CTL_RC_REL (1 << 1) > +#define PCIE_CONTROL_RST_CTL_PHY_REL (1 << 0) > +#define PCIE_CONTROL_RST_CTL_RCPHY_REL (PCIE_CONTROL_RST_CTL_RC_REL | PCIE_CONTROL_RST_CTL_PHY_REL) > + > +#define PCIE_CONTROL_RST_STS_RC_ST (1 << 2) > +#define PCIE_CONTROL_RST_STS_PHY_ST (1 << 1) > +#define PCIE_CONTROL_RST_STS_PLL_ST (1 << 0) > +#define PCIE_CONTROL_RST_STS_RCPHYPLL_OUT (PCIE_CONTROL_RST_STS_RC_ST | PCIE_CONTROL_RST_STS_PHY_ST | PCIE_CONTROL_RST_STS_PLL_ST) > + > +#define VEXPRESS_BASIC_STATUS 0x18 > +#define LINK_UP 0xff > + > +#endif > -- > 2.9.3 > ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 10/13] Platforms/Juno: switch to generic PCI host bridge driver 2017-03-31 14:15 [PATCH v2 00/13] EDK2 spring cleaning -- OpenPlatformPkg edition Ard Biesheuvel ` (8 preceding siblings ...) 2017-03-31 14:15 ` [PATCH v2 09/13] Platforms/Juno: add PciHostBridgeLib implementation Ard Biesheuvel @ 2017-03-31 14:19 ` Ard Biesheuvel 2017-03-31 14:19 ` [PATCH v2 11/13] Platforms/Juno: remove BdsLib dependency Ard Biesheuvel ` (2 more replies) 9 siblings, 3 replies; 15+ messages in thread From: Ard Biesheuvel @ 2017-03-31 14:19 UTC (permalink / raw) To: edk2-devel, leif.lindholm, ryan.harkin; +Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/ARM/Juno/ArmJuno.dsc | 17 +++++++++++------ Platforms/ARM/Juno/ArmJuno.fdf | 4 ++-- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 141616e13234..b7b1fb8c8935 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -66,6 +66,10 @@ [LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER] PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf + PciHostBridgeLib|OpenPlatformPkg/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf [BuildOptions] *_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmJunoPkg/Include @@ -143,13 +147,17 @@ # PLDA PCI Root Complex # gArmTokenSpaceGuid.PcdPciBusMax|255 - gArmTokenSpaceGuid.PcdPciIoBase|0x5f800000 + gArmTokenSpaceGuid.PcdPciIoBase|0x0 gArmTokenSpaceGuid.PcdPciIoSize|0x00800000 gArmTokenSpaceGuid.PcdPciMmio32Base|0x50000000 gArmTokenSpaceGuid.PcdPciMmio32Size|0x08000000 gArmTokenSpaceGuid.PcdPciMmio64Base|0x4000000000 gArmTokenSpaceGuid.PcdPciMmio64Size|0x100000000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x40000000 + gArmTokenSpaceGuid.PcdPciIoTranslation|0x5f800000 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 + # List of Device Paths that support BootMonFs gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)" @@ -270,16 +278,13 @@ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf # Required by PCI - UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf # # PCI Support # MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf { - <LibraryClasses> - DmaLib|EmbeddedPkg/Library/NullDmaLib/NullDmaLib.inf - } + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf # # SATA Controller diff --git a/Platforms/ARM/Juno/ArmJuno.fdf b/Platforms/ARM/Juno/ArmJuno.fdf index 3f96266fb625..7de995a255b1 100644 --- a/Platforms/ARM/Juno/ArmJuno.fdf +++ b/Platforms/ARM/Juno/ArmJuno.fdf @@ -140,7 +140,7 @@ FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270092 INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf # Required by PCI - INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf # FV FileSystem INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf @@ -161,7 +161,7 @@ FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270092 # PCI Support # INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - INF ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf # # SATA Controller -- 2.9.3 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 11/13] Platforms/Juno: remove BdsLib dependency 2017-03-31 14:19 ` [PATCH v2 10/13] Platforms/Juno: switch to generic PCI host bridge driver Ard Biesheuvel @ 2017-03-31 14:19 ` Ard Biesheuvel 2017-03-31 14:19 ` [PATCH v2 12/13] Platforms/Juno: add DtPlatformDtbLoaderLib implementation Ard Biesheuvel 2017-03-31 14:19 ` [PATCH v2 13/13] Platforms/Juno: switch to DtPlatformDxe Ard Biesheuvel 2 siblings, 0 replies; 15+ messages in thread From: Ard Biesheuvel @ 2017-03-31 14:19 UTC (permalink / raw) To: edk2-devel, leif.lindholm, ryan.harkin; +Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/ARM/Juno/ArmJuno.dsc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index b7b1fb8c8935..4ff2246822e6 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -318,10 +318,7 @@ # # Juno platform driver # - ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf { - <LibraryClasses> - BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf - } + ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf # # SMBIOS/DMI -- 2.9.3 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 12/13] Platforms/Juno: add DtPlatformDtbLoaderLib implementation 2017-03-31 14:19 ` [PATCH v2 10/13] Platforms/Juno: switch to generic PCI host bridge driver Ard Biesheuvel 2017-03-31 14:19 ` [PATCH v2 11/13] Platforms/Juno: remove BdsLib dependency Ard Biesheuvel @ 2017-03-31 14:19 ` Ard Biesheuvel 2017-03-31 14:19 ` [PATCH v2 13/13] Platforms/Juno: switch to DtPlatformDxe Ard Biesheuvel 2 siblings, 0 replies; 15+ messages in thread From: Ard Biesheuvel @ 2017-03-31 14:19 UTC (permalink / raw) To: edk2-devel, leif.lindholm, ryan.harkin; +Cc: Ard Biesheuvel In preparation of switching to DtPlatformDxe to supply the device tree image to the OS, add an implementation of DtPlatformDtbLoaderLib that loads the correct version from an FV. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/ARM/Juno/Library/JunoDtPlatformDtbLoaderLib/JunoDtPlatformDtbLoaderLib.c | 71 ++++++++++++++++++++ Platforms/ARM/Juno/Library/JunoDtPlatformDtbLoaderLib/JunoDtPlatformDtbLoaderLib.inf | 38 +++++++++++ 2 files changed, 109 insertions(+) diff --git a/Platforms/ARM/Juno/Library/JunoDtPlatformDtbLoaderLib/JunoDtPlatformDtbLoaderLib.c b/Platforms/ARM/Juno/Library/JunoDtPlatformDtbLoaderLib/JunoDtPlatformDtbLoaderLib.c new file mode 100644 index 000000000000..8b4d1cbecffb --- /dev/null +++ b/Platforms/ARM/Juno/Library/JunoDtPlatformDtbLoaderLib/JunoDtPlatformDtbLoaderLib.c @@ -0,0 +1,71 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <PiDxe.h> + +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/DxeServicesLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> + +#include "ArmPlatform.h" + +/** + Return a pool allocated copy of the DTB image that is appropriate for + booting the current platform via DT. + + @param[out] Dtb Pointer to the DTB copy + @param[out] DtbSize Size of the DTB copy + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_NOT_FOUND No suitable DTB image could be located + @retval EFI_OUT_OF_RESOURCES No pool memory available + +**/ +EFI_STATUS +EFIAPI +DtPlatformLoadDtb ( + OUT VOID **Dtb, + OUT UINTN *DtbSize + ) +{ + EFI_STATUS Status; + VOID *OrigDtb; + VOID *CopyDtb; + UINTN OrigDtbSize; + UINT32 JunoRevision; + + GetJunoRevision(JunoRevision); + ASSERT (JunoRevision >= JUNO_REVISION_R0 && JunoRevision <= JUNO_REVISION_R2); + if (JunoRevision < JUNO_REVISION_R0 || JunoRevision > JUNO_REVISION_R2) { + return EFI_NOT_FOUND; + } + + Status = GetSectionFromAnyFv (&gDtPlatformDefaultDtbFileGuid, + EFI_SECTION_RAW, (UINTN)JunoRevision - 1, &OrigDtb, &OrigDtbSize); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + CopyDtb = AllocateCopyPool (OrigDtbSize, OrigDtb); + if (CopyDtb == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + *Dtb = CopyDtb; + *DtbSize = OrigDtbSize; + + return EFI_SUCCESS; +} diff --git a/Platforms/ARM/Juno/Library/JunoDtPlatformDtbLoaderLib/JunoDtPlatformDtbLoaderLib.inf b/Platforms/ARM/Juno/Library/JunoDtPlatformDtbLoaderLib/JunoDtPlatformDtbLoaderLib.inf new file mode 100644 index 000000000000..8018278546fe --- /dev/null +++ b/Platforms/ARM/Juno/Library/JunoDtPlatformDtbLoaderLib/JunoDtPlatformDtbLoaderLib.inf @@ -0,0 +1,38 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = JunoDtPlatformDtbLoaderLib + FILE_GUID = 050d6041-1508-4ae7-a69f-250155ccb567 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = DtPlatformDtbLoaderLib|DXE_DRIVER + +[Sources] + JunoDtPlatformDtbLoaderLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + BaseLib + DxeServicesLib + IoLib + MemoryAllocationLib + +[Guids] + gDtPlatformDefaultDtbFileGuid -- 2.9.3 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 13/13] Platforms/Juno: switch to DtPlatformDxe 2017-03-31 14:19 ` [PATCH v2 10/13] Platforms/Juno: switch to generic PCI host bridge driver Ard Biesheuvel 2017-03-31 14:19 ` [PATCH v2 11/13] Platforms/Juno: remove BdsLib dependency Ard Biesheuvel 2017-03-31 14:19 ` [PATCH v2 12/13] Platforms/Juno: add DtPlatformDtbLoaderLib implementation Ard Biesheuvel @ 2017-03-31 14:19 ` Ard Biesheuvel 2 siblings, 0 replies; 15+ messages in thread From: Ard Biesheuvel @ 2017-03-31 14:19 UTC (permalink / raw) To: edk2-devel, leif.lindholm, ryan.harkin; +Cc: Ard Biesheuvel Switch to DtPLatformDxe, which uses embedded DTB binaries, or ACPI, but does not have the elaborate (but awkward) tooling to load FDT files from device paths. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/ARM/Juno/ArmJuno.dsc | 15 +++------------ Platforms/ARM/Juno/ArmJuno.fdf | 11 ++++++++--- Platforms/ARM/Juno/DeviceTree/juno-r1.dtb | Bin 0 -> 23627 bytes Platforms/ARM/Juno/DeviceTree/juno-r2.dtb | Bin 0 -> 23627 bytes Platforms/ARM/Juno/DeviceTree/juno.dtb | Bin 0 -> 22431 bytes 5 files changed, 11 insertions(+), 15 deletions(-) diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 4ff2246822e6..683992af32e9 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -50,6 +50,8 @@ # USB Requirements UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + DtPlatformDtbLoaderLib|OpenPlatformPkg/Platforms/ARM/Juno/Library/JunoDtPlatformDtbLoaderLib/JunoDtPlatformDtbLoaderLib.inf + [LibraryClasses.common.SEC] PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf @@ -196,14 +198,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|1080 [PcdsDynamicDefault.common] - # - # The size of a dynamic PCD of the (VOID*) type can not be increased at run - # time from its size at build time. Set the "PcdFdtDevicePaths" PCD to a 128 - # character "empty" string, to allow to be able to set FDT text device paths - # up to 128 characters long. - # - gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths|L" " - # Not all Juno platforms support PCI. This dynamic PCD disables or enable # PCI support. gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE @@ -343,10 +337,7 @@ # # FDT installation # - EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf { - <LibraryClasses> - BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf - } + EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf [Components.AARCH64] # diff --git a/Platforms/ARM/Juno/ArmJuno.fdf b/Platforms/ARM/Juno/ArmJuno.fdf index 7de995a255b1..2f6cf62558ea 100644 --- a/Platforms/ARM/Juno/ArmJuno.fdf +++ b/Platforms/ARM/Juno/ArmJuno.fdf @@ -220,9 +220,14 @@ FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270092 # # FDT installation # - # The UEFI driver is at the end of the list of the driver to be dispatched - # after the device drivers (eg: Ethernet) to ensure we have support for them. - INF EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf + INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf + + # builtin device tree binaries -- for rev 0/1/2, respectively. + FILE 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end of thread, other threads:[~2017-04-04 8:31 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-03-31 14:15 [PATCH v2 00/13] EDK2 spring cleaning -- OpenPlatformPkg edition Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 01/13] Platforms/VExpress: remove unused logo PCD Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 02/13] Platforms/VExpress: remove unused StatusCode references Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 03/13] Platforms/VExpress: get rid of Tiano compression Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 04/13] Platforms/VExpress: remove BdsLib library class resolutions Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 05/13] Platforms/TC2: move to new DtPlatformDxe driver Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 06/13] Platforms/FVP: add DtPlatformDtbLoaderLib implementation Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 07/13] Platforms/FVP-AArch64: switch to simpler DT platform driver Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 08/13] Platforms/Juno: add non-discoverable device driver and library Ard Biesheuvel 2017-03-31 14:15 ` [PATCH v2 09/13] Platforms/Juno: add PciHostBridgeLib implementation Ard Biesheuvel 2017-04-04 8:31 ` Ard Biesheuvel 2017-03-31 14:19 ` [PATCH v2 10/13] Platforms/Juno: switch to generic PCI host bridge driver Ard Biesheuvel 2017-03-31 14:19 ` [PATCH v2 11/13] Platforms/Juno: remove BdsLib dependency Ard Biesheuvel 2017-03-31 14:19 ` [PATCH v2 12/13] Platforms/Juno: add DtPlatformDtbLoaderLib implementation Ard Biesheuvel 2017-03-31 14:19 ` [PATCH v2 13/13] Platforms/Juno: switch to DtPlatformDxe Ard Biesheuvel
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