From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::243; helo=mail-it0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x243.google.com (mail-it0-x243.google.com [IPv6:2607:f8b0:4001:c0b::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 01A452214E329 for ; Mon, 11 Dec 2017 09:52:32 -0800 (PST) Received: by mail-it0-x243.google.com with SMTP id o130so13722344itg.0 for ; Mon, 11 Dec 2017 09:57:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=j9h2OPliH4SGeGXEOBpT6QuMRP4uR2E+kMNt1rGJkxE=; b=ZydLr08WC0iQa0T31bg/IVkW1HXiGG1VVH4/42ND0mp6GdhUUcb8q0JfguArgQTtBv JmCSxLgdPd7C5ATwM1sX1nIzWUYevS/l7IGh5aniGJC2m7ten9RvO8nKrA+q/ydcw/AF xGo3nz4UPhXqQMXkAQs5RgqFt2200f+k51eqY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=j9h2OPliH4SGeGXEOBpT6QuMRP4uR2E+kMNt1rGJkxE=; b=F/6V87Iy68guctEVPNN9HW4AVVtah85giq6T46bOp4pvb3nXqFuf+kjxr30C/10v8D rt+Kj15Dqni6z/iJhew+p6/8zLsn98+kXXUzqUmUApQXdvfluzb3Wl2xIUUMMLN6kjws M3QNMWq+6I4q74NM5uusw0dhQPqkI2gPyjx3LUXhHFbQ9hs7DAFLwwrpC5kUT30U2S34 B0xUor1cDslmJWrzdeleZqxsyiqymYRhh05icfI1t6aIOA9aURP7bME7AOwprFmleF+g gZ0Thhi2QhTYhLscGbxiLK/wv2UyGPd4LjFx0A9MXaDnkFfeA3aa9C6sPzGkOE4Hfih9 RREQ== X-Gm-Message-State: AKGB3mKx86MILNJEW04alMT3d3CU9JWu0VjqaD8TWJKHbn7hBzWQ6jBa kjJdxOwM7U6N/5/13Qz1r+7oLWs5r9RHfHimqZGaFFwa X-Google-Smtp-Source: ACJfBovk3clKtjrO2KYezfbIJlXMO/R32NT33J7amEaXY3A/c+WcagdhNctlK4XfssRpNot3Wk6gyb6UNdTE0eJqn3o= X-Received: by 10.107.2.137 with SMTP id 131mr1702950ioc.186.1513015030132; Mon, 11 Dec 2017 09:57:10 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.104.16 with HTTP; Mon, 11 Dec 2017 09:57:09 -0800 (PST) In-Reply-To: <20171211154204.lcdzebwhub6yiwy6@bivouac.eciton.net> References: <20171208182732.8891-1-ard.biesheuvel@linaro.org> <20171211154204.lcdzebwhub6yiwy6@bivouac.eciton.net> From: Ard Biesheuvel Date: Mon, 11 Dec 2017 17:57:09 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" Subject: Re: [PATCH] ArmPlatformPkg: retire obsolete PCDs X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Dec 2017 17:52:33 -0000 Content-Type: text/plain; charset="UTF-8" On 11 December 2017 at 15:42, Leif Lindholm wrote: > On Fri, Dec 08, 2017 at 06:27:32PM +0000, Ard Biesheuvel wrote: >> Retire a whole bunch of ArmPlatformPkg PCDs that are either related >> to the ARM BDS, to secure world execution or to stuff that has been >> migrated to edk2-platforms. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel > > Commenting out-of-order... > By the time we get to this, should we not also delete > ## PL111 Lcd & HdLcd > gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026 > gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027 > ? > Nope, as you just found out yourself. >> --- >> ArmPlatformPkg/ArmPlatformPkg.dec | 41 -------------------- >> 1 file changed, 41 deletions(-) >> >> diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec >> index b33b6e630d85..7cec775abeee 100644 >> --- a/ArmPlatformPkg/ArmPlatformPkg.dec >> +++ b/ArmPlatformPkg/ArmPlatformPkg.dec >> @@ -45,13 +45,7 @@ [Guids.common] >> # >> gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } } >> >> - gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } } >> - >> [PcdsFeatureFlag.common] >> - # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0. >> - gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012 >> - >> - gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001 >> gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004 >> >> gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C >> @@ -60,18 +54,10 @@ [PcdsFeatureFlag.common] >> # we assume the OS will handle the FrameBuffer from the UEFI GOP information. >> gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D >> >> - # Enable Legacy Linux support in the BDS >> - gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|FALSE|BOOLEAN|0x0000002E >> - >> [PcdsFixedAtBuild.common] >> gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039 >> gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038 >> >> - # Stack for CPU Cores in Secure Mode >> - gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT64|0x00000005 >> - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036 >> - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006 >> - >> # Stack for CPU Cores in Non Secure Mode >> gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009 >> gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037 >> @@ -80,9 +66,6 @@ [PcdsFixedAtBuild.common] >> # Size of the region used by UEFI in permanent memory (Reserved 128MB by default) >> gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015 >> >> - # Boot Monitor FileSystem >> - gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A >> - >> # >> # ARM Primecells >> # >> @@ -114,33 +97,9 @@ [PcdsFixedAtBuild.common] >> gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028 >> gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029 >> >> - # >> - # BDS - Boot Manager >> - # >> - gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019 >> - gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C >> - gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D >> - gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F >> - >> - gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B >> - gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C >> - >> [PcdsFixedAtBuild.common,PcdsDynamic.common] >> ## PL031 RealTimeClock >> gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024 >> gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022 >> >> gArmPlatformTokenSpaceGuid.PcdWatchdogCount|0x0|UINT32|0x00000033 >> - >> -[PcdsFixedAtBuild.ARM] >> - # Stack for CPU Cores in Secure Monitor Mode >> - gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007 >> - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008 >> - >> -[PcdsFixedAtBuild.AARCH64] >> - # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64. >> - # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize >> - # and PcdCPUCoreSecSecondaryStackSize >> - gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007 >> - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008 >> - >> -- >> 2.11.0 >>