From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::241; helo=mail-io0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x241.google.com (mail-io0-x241.google.com [IPv6:2607:f8b0:4001:c06::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6B2ED20971756 for ; Fri, 1 Jun 2018 03:18:43 -0700 (PDT) Received: by mail-io0-x241.google.com with SMTP id g7-v6so5260217ioh.11 for ; Fri, 01 Jun 2018 03:18:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=9gJp9jKRCGOBDON4mg8j6sm/tV24N1NufcQNJV51JL0=; b=QS+9GhV7tDwIQM9KERhI3mfmGWTFbhF7E4CJR2uTd3NboehgAxPsyaSSIyLwToqqnS XQ/UvdDTQ5w/SewXckI2Vwa/vI2tJYVKcgIx5Ym2gtNM0Pzz8RfLThhkabhS9tQkB8bY ryLatwrM48icod0KZIvPrMPyynMKo0kGqzwE4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=9gJp9jKRCGOBDON4mg8j6sm/tV24N1NufcQNJV51JL0=; b=M1iqZ+gS5HTN7eM2eoF/1Fk9sG+dXGdl1gUFfaiY+M46cVPLJrhQVSO330C2ytnWwg O2iv/tMB524ICek5VjKUIEzbO26wTIy3N7y/xgababWGwzqlD8gf/Pf/pbDskg+eCOLW dDA9lXENYfeHL0aMu8x3UXFDJImWu9VOrmSQhuz0jysP2tf1KuIN7PG81OS9fpUPiqPR ncYWTiX0qspa+VWSt8KRj27KxVrn1KlFNkaw5zWyyo1mwgZ4fCHEg4MAwh1s19Wo5PHH RRHWbfF6+Gp79VLZgzMCue5k+lxa2atZK4aRaOV26jVozNNFbRedLE66MGbnP+51Xb3o 9xwQ== X-Gm-Message-State: ALKqPwfCAd47vanIbuv4raY2C81wfH1JHMbfoW4hp8Nd0+cOF4N8gglw AjUCpbDsArwnqL9z4E26h16QBs1L4s+/LlRrVPKWKg== X-Google-Smtp-Source: ADUXVKK1wcllzLUg9DLaSlCgFtNE+88d6pwJTtlOiEp37frOrTlLD4PZikbzyRM9JjKXEl2VlZ6rwEs6PFay51gOtdE= X-Received: by 2002:a6b:dd0b:: with SMTP id f11-v6mr4067592ioc.173.1527848322712; Fri, 01 Jun 2018 03:18:42 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:bb86:0:0:0:0:0 with HTTP; Fri, 1 Jun 2018 03:18:42 -0700 (PDT) In-Reply-To: <20180531091438.wwfw2ymrhwte55hr@bivouac.eciton.net> References: <20180530181929.5066-1-ard.biesheuvel@linaro.org> <20180530181929.5066-3-ard.biesheuvel@linaro.org> <20180531091438.wwfw2ymrhwte55hr@bivouac.eciton.net> From: Ard Biesheuvel Date: Fri, 1 Jun 2018 12:18:42 +0200 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Masahisa Kojima Subject: Re: [PATCH edk2-platforms 2/3] Silicon/Socionext/SynQuacer/Stage2Tables: add north SMMU level 3 table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Jun 2018 10:18:43 -0000 Content-Type: text/plain; charset="UTF-8" On 31 May 2018 at 11:14, Leif Lindholm wrote: > On Wed, May 30, 2018 at 08:19:28PM +0200, Ard Biesheuvel wrote: >> Extend the static stage 2 page tables with a set of level 3 tables that >> describe the ECAM space in a manner that allows the north SMMU to be used >> to make the ECAM space appear sane to the CPUs. >> >> It is up to the secure firmware to manipulate the north SMMU page tables > > s/secure/EL3/ or s/secure/Secure/? > > With either of those: > Reviewed-by: Leif Lindholm > Thanks Pushed as ba32985a0631 > >> so that the level 2 block entries corresponding with busses #0 .. #1 in >> the respective config spaces of PCI0 and PCI1 are replaced with table >> entries pointing to the level 3 tables added by this patch. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel >> --- >> Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 35 +++++++++++++++----- >> 1 file changed, 26 insertions(+), 9 deletions(-) >> >> diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S >> index 313ef3c56abc..af55f27bca47 100644 >> --- a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S >> +++ b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S >> @@ -20,15 +20,17 @@ >> * the SoC. >> */ >> >> -#define TT_S2_CONT_SHIFT 52 >> -#define TT_S2_AF (0x1 << 10) >> -#define TT_S2_SH_NON_SHAREABLE (0x0 << 8) >> -#define TT_S2_AP_RW (0x3 << 6) >> -#define TT_S2_MEMATTR_DEVICE_nGRE (0x2 << 2) >> -#define TT_S2_MEMATTR_MEMORY_WB (0xf << 2) >> -#define TT_S2_TABLE (0x3 << 0) >> -#define TT_S2_L3_PAGE (0x1 << 1) >> -#define TT_S2_VALID (0x1 << 0) >> +#define TT_S2_CONT_SHIFT 52 >> +#define TT_S2_AF (0x1 << 10) >> +#define TT_S2_SH_NON_SHAREABLE (0x0 << 8) >> +#define TT_S2_AP_RO (0x1 << 6) >> +#define TT_S2_AP_RW (0x3 << 6) >> +#define TT_S2_MEMATTR_DEVICE_nGRE (0x2 << 2) >> +#define TT_S2_MEMATTR_DEVICE_nGnRE (0x1 << 2) >> +#define TT_S2_MEMATTR_MEMORY_WB (0xf << 2) >> +#define TT_S2_TABLE (0x3 << 0) >> +#define TT_S2_L3_PAGE (0x1 << 1) >> +#define TT_S2_VALID (0x1 << 0) >> >> .altmacro >> .macro for, start, count, do, arg2, arg3, arg4 >> @@ -58,6 +60,12 @@ >> TT_S2_L3_PAGE | TT_S2_VALID | (\cont << TT_S2_CONT_SHIFT) >> .endm >> >> + .macro smmu_l3_entry, base, offset=0, ignore=0 >> + .quad ((\base << 12) + \offset) | TT_S2_AF | TT_S2_AP_RO | \ >> + TT_S2_SH_NON_SHAREABLE | TT_S2_MEMATTR_DEVICE_nGnRE | \ >> + TT_S2_L3_PAGE | TT_S2_VALID >> + .endm >> + >> .section ".rodata", "a", %progbits >> /* level 1 */ >> s2_mem_entry 0 /* 0x0000_0000 - 0x3fff_ffff */ >> @@ -86,3 +94,12 @@ >> 3:for 0, 8, s2_l3_entry, 0x70000000 >> for 0, 8, s2_l3_entry, 0x70010000 /* hide device #1 */ >> for 0, 496, s2_l3_entry, 0x70010000, 1 >> + >> + /* level 3 for north SMMU */ >> + .org 0x6000 >> + for 0, 8, smmu_l3_entry, 0xc00060000000 >> + for 0, 8, smmu_l3_entry, 0xc00060010000 /* hide device #1 */ >> + for 0, 496, smmu_l3_entry, 0xc00060010000 >> + for 0, 8, smmu_l3_entry, 0x800070000000 >> + for 0, 8, smmu_l3_entry, 0x800070010000 /* hide device #1 */ >> + for 0, 496, smmu_l3_entry, 0x800070010000 >> -- >> 2.17.0 >>