From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::231; helo=mail-it0-x231.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x231.google.com (mail-it0-x231.google.com [IPv6:2607:f8b0:4001:c0b::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E17552219BC8F for ; Wed, 20 Dec 2017 07:21:58 -0800 (PST) Received: by mail-it0-x231.google.com with SMTP id r6so7246524itr.3 for ; Wed, 20 Dec 2017 07:26:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=ShVG9qJEwYutwhZl3YfEUB/bceJ9XTOvzUEnZxI326Y=; b=O2U30L76J5fmAnqD0BxPHJkasdoNMskM3bGo5F9lZSPMF9227PBHxw5M/h5NKMSQnL QTI2Vlk20JqPYi5qqE+gRikQe620AIlMsRfYtiB5w6oUlLJvATyTsGJnzdOAxon86mhZ +Oa4YpaJqFHMNd+9ImElKS7PuNP9jIWqbS2WI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=ShVG9qJEwYutwhZl3YfEUB/bceJ9XTOvzUEnZxI326Y=; b=ekwdB6UOtIBJNayNRPH368ikCMuYka5AO0xO5H9MKE+5YNtSJ43XxXL0XWcUdCvznS /F7016FZ8xMfdpTbCZg959ntNXdJqS5+/alWv6TvjmiB+vBUb19rvDF56I0hMg5yiRjq GpjCZIkGvjL/7kubX+oYXdjILfMLQbkmb+4vam3cMFd6LuuQIfrSQ1Kc46lRr54l9PdY alIuJL8I/KioVON79ttUaLFIgx+U/klpg7lzIhjf+hHuY4kAY9g5kOOedQV/HTKoRM+P g9pC5lB+7jUtWpGE97uNvNrLB1aH8+rXFqf+f19KG+eBD7kISJm8zhMjLETw6UgPOxUg 9WUw== X-Gm-Message-State: AKGB3mLpQcKDITVtEQEyEfSMk3nVRsCH10hssr9lPlYIgkWtftSON4AX Z/CqPCQ9c4rlPnRTI/V/YlA+kJnA6eh5tR4bhMCIcQ== X-Google-Smtp-Source: ACJfBosID6tAPYo8fXenPmdUncjGIzvoHYB5BUUhkAlJLB1j2At8eBBN4YOSUsEo3cRsv2kpWK+3bD6YfgOUwk/+f+E= X-Received: by 10.36.78.212 with SMTP id r203mr8305408ita.58.1513783605752; Wed, 20 Dec 2017 07:26:45 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.52.14 with HTTP; Wed, 20 Dec 2017 07:26:45 -0800 (PST) In-Reply-To: <20171220151704.GA2482@iwish> References: <1513758078-99534-1-git-send-email-heyi.guo@linaro.org> <20171220151704.GA2482@iwish> From: Ard Biesheuvel Date: Wed, 20 Dec 2017 15:26:45 +0000 Message-ID: To: gary guo Cc: linaro-uefi , "edk2-devel@lists.01.org" , Star Zeng , Eric Dong , Ruiyu Ni , Jason Zhang Subject: Re: [RFC] MdeModulePkg/PciHostBridge: Add address translation support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Dec 2017 15:21:59 -0000 Content-Type: text/plain; charset="UTF-8" On 20 December 2017 at 15:17, gary guo wrote: > On Wed, Dec 20, 2017 at 09:13:58AM +0000, Ard Biesheuvel wrote: >> Hi Heyi, >> >> On 20 December 2017 at 08:21, Heyi Guo wrote: >> > PCIe on some ARM platforms requires address translation, not only for >> > legacy IO access, but also for 32bit memory BAR access as well. There >> > will be "Address Translation Unit" or something similar in PCI host >> > bridges to translation CPU address to PCI address and vice versa. So >> > we think it may be useful to add address translation support to the >> > generic PCI host bridge driver. >> > >> >> I agree. While unusual on a PC, it is quite common on other >> architectures to have more complex non 1:1 topologies, which currently >> require a forked PciHostBridgeDxe driver with local changes applied. >> >> > This RFC only contains one minor change to the definition of >> > PciHostBridgeLib, and there certainly will be a lot of other changes >> > to make it work, including: >> > >> > 1. Use CPU address for GCD space add and allocate operations, instead >> > of PCI address; also IO space will be changed to memory space if >> > translation exists. >> > >> >> For I/O space, the translation should simply be applied to the I/O >> range. I don't think it makes sense to use memory space here, given >> that it is specific to architectures that lack native port I/O. >> > > I made an assumption here that platforms supporting real port IO space > do not need address translation, like IA32 and X64, and port IO > translation implies the platform does not support real port IO space. > This may be a reasonable assumption. But I still think it is better not to encode any assumptions in the first place. > Indeed the assumption is not so "generic", so I'll agree if you > recommend to support IO to IO translation as well. But I still hope to > have IO to memory translation support in PCI host bridge driver, > rather than in CPU IO protocol, since the faked IO space might only be > used for PCI host bridge and we may have overlapping IO ranges for > each host bridge, which is compatible with PCIe specification and PCIe > ACPI description. > That is fine. Under UEFI, these will translate to non-overlapping I/O spaces in the CPU's view. Under the OS, this could be totally different. For example, RC0 IO 0x0000 .. 0xffff -> CPU 0x00000 .. 0x0ffff RC1 IO 0x0000 .. 0xffff -> CPU 0x10000 .. 0x1ffff This is very similar to how MMIO translation works, and makes I/O devices behind the host bridges uniquely addressable for drivers. For our understanding, could you share the host bridge configuration that you are targetting? Thanks, Ard. > How about adding a flag to indicate whether port IO is translated to > real port IO space or system memory space? > > Thanks and regards, > > Heyi > >> > 2. RootBridgeIoMemRead/Write, RootBridgeIoRead/Write need to get >> > translation of the corresponding aperture, add the translation to the >> > input address, and then call CpuIo2 protocol; IO access will also be >> > converted to memory access if IO translation exists. >> > >> >> Again, why is this necessary? A host bridge that implements a non 1:1 >> translation for port I/O ranges may be part of a system that has >> native port I/O, and so the translation should be based on that. >> >> > 3. RootBridgeIoConfiguration needs to fill AddrTranslationOffset in >> > the discriptor. >> > >> >> Indeed. Note that this has been a source of much confusion lately, >> should we should discuss this carefully before spending time on an >> implementation. >> >> > If it makes sense, then I'll continue to prepare the formal patch. >> > >> > Any comments? >> > >> > Thanks, >> > >> > Gary (Heyi Guo) >> > >> > Cc: Star Zeng >> > Cc: Eric Dong >> > Cc: Ruiyu Ni >> > Cc: Ard Biesheuvel >> > Cc: Jason Zhang >> > >> > --- >> > MdeModulePkg/Include/Library/PciHostBridgeLib.h | 1 + >> > 1 file changed, 1 insertion(+) >> > >> > diff --git a/MdeModulePkg/Include/Library/PciHostBridgeLib.h b/MdeModulePkg/Include/Library/PciHostBridgeLib.h >> > index d42e9ec..b9e8c0f 100644 >> > --- a/MdeModulePkg/Include/Library/PciHostBridgeLib.h >> > +++ b/MdeModulePkg/Include/Library/PciHostBridgeLib.h >> > @@ -22,6 +22,7 @@ >> > typedef struct { >> > UINT64 Base; >> > UINT64 Limit; >> > + UINT64 Translation; >> > } PCI_ROOT_BRIDGE_APERTURE; >> > >> > typedef struct { >> > -- >> > 2.7.4 >> >