From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::242; helo=mail-it0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x242.google.com (mail-it0-x242.google.com [IPv6:2607:f8b0:4001:c0b::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 96C7D21124B07 for ; Fri, 7 Sep 2018 04:06:38 -0700 (PDT) Received: by mail-it0-x242.google.com with SMTP id h23-v6so19373798ita.5 for ; Fri, 07 Sep 2018 04:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=Zpjga7Xl9tPRSErtwRJBGqlBe7AgFe1EB+sOuSBlXm4=; b=CJkEPtAqNVN7ixz/2lVF23c7L8UA6cYQEAeI4m/xkzdifB0TRfX1zzADJAHsWvabae bCpDCPEJxbe+Utk6L2cb7RIany7yQ40Pc0nBiyZdI2gKvgHwrywr0c0Ch2mPXJ3JICaq Yp6F/1TglrtW0ceYTZK9xBnvb0OlZ0jRWRA2M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=Zpjga7Xl9tPRSErtwRJBGqlBe7AgFe1EB+sOuSBlXm4=; b=Qx1PxiVnD3HTe6qB6LpsHUoVa4RNXOuNaXwOr0ETQjAc1wKRbf2ZryYzcgGapqQMVh 27ILSeDOQ3WFjdQ56oDDdtMxC77yR/lt7fBN4+Irt+zE+zEDAsznJi0bUmud/YwI76Nl Yin/ol4AmnZqc+udRgfVrrkK1Nisk23WFxRbVC1ID0zKNKZqkeHRISIkSCsvtsoCqGlu bGSz0+e6/4MqCybl2fK5KWbebcDNc4dGNAyTm9X9nyJ2EbKGNjquCrZqPoK53+onW91N G5e3PcmVGTZHSFGE243mOlCKQOAWD7ljuBYOZDl4ULY7uwMVpsWjyQA/HUOgcWKtUWy8 w93Q== X-Gm-Message-State: APzg51DZu2Q8k2tez1weDZpuJzSF5yGpJ4clspre9JTfWrrzQIoeLGfV D9RIw/R+7etyHwjF4tlh1A+grLeaeEqSf2+iA65CaNRqLug= X-Google-Smtp-Source: ANB0VdY9LTBnD1dfSghg92cRMFlkTMeIev+ZicztUFIOo4CDZhFdUa1WaZEwGZpnfi2up60Njw6c+1XWrzHsGimLIgc= X-Received: by 2002:a02:1515:: with SMTP id j21-v6mr6289759jad.2.1536318397584; Fri, 07 Sep 2018 04:06:37 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:1c06:0:0:0:0:0 with HTTP; Fri, 7 Sep 2018 04:06:37 -0700 (PDT) In-Reply-To: <1536311416-2751-4-git-send-email-mw@semihalf.com> References: <1536311416-2751-1-git-send-email-mw@semihalf.com> <1536311416-2751-4-git-send-email-mw@semihalf.com> From: Ard Biesheuvel Date: Fri, 7 Sep 2018 13:06:37 +0200 Message-ID: To: Marcin Wojtas Cc: "edk2-devel@lists.01.org" , "Tian, Feng" , "Kinney, Michael D" , "Gao, Liming" , Leif Lindholm , Nadav Haklai , =?UTF-8?B?SmFuIETEhWJyb8Wb?= , Tomasz Michalec Subject: Re: [PATCH v2 3/4] MdeModulePkg/SdMmcPciHcDxe: Fix SdMmcHcReset to set only necesery bits X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 07 Sep 2018 11:06:38 -0000 Content-Type: text/plain; charset="UTF-8" On 7 September 2018 at 11:10, Marcin Wojtas wrote: > From: Tomasz Michalec > > SdMmcHcReset used to set all bits of Software Reset Register to 1 > including reserved ones. > > Now only first bit is set which means "Software Reset for All". > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 5 +++++ > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 6 +++--- > 2 files changed, 8 insertions(+), 3 deletions(-) > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > index e3fadb5..ec90d1e 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > @@ -68,6 +68,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > #define SD_MMC_HC_HOST_CTRL1_HS_ENABLE (1 << 2) > > // > +// SD Software Reset Register bits description > +// > +#define SD_MMC_HC_SW_RST_ALL (1 << 0) Please use BIT0 here > + > +// > // The transfer modes supported by SD Host Controller > // Simplified Spec 3.0 Table 1-2 > // > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > index 9672b5b..9d9bca8 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > @@ -454,8 +454,8 @@ SdMmcHcReset ( > } > > PciIo = Private->PciIo; > - SwReset = 0xFF; > - Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_SW_RST, FALSE, sizeof (SwReset), &SwReset); > + SwReset = SD_MMC_HC_SW_RST_ALL; > + Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset); > > if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write full 1 fails: %r\n", Status)); > @@ -467,7 +467,7 @@ SdMmcHcReset ( > Slot, > SD_MMC_HC_SW_RST, > sizeof (SwReset), > - 0xFF, > + SD_MMC_HC_SW_RST_ALL, > 0x00, > SD_MMC_HC_GENERIC_TIMEOUT > ); > -- > 2.7.4 >