From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::242; helo=mail-io0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x242.google.com (mail-io0-x242.google.com [IPv6:2607:f8b0:4001:c06::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0B869223FCF46 for ; Thu, 15 Mar 2018 13:54:05 -0700 (PDT) Received: by mail-io0-x242.google.com with SMTP id k21so10204863ioc.2 for ; Thu, 15 Mar 2018 14:00:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=eD3YJscYhVTGZeYsWk7WtJsvt2DVVsRSD/cXsJZc72k=; b=g7pylEYu2u5Hhzb8iz+2hbscv8UFJJJST4zFyQQawPq4q+JFUvYM/+NxlzeIc5sZli Rg4EXKCh0sEyd9CBwHebw5kHQvseoE5jr/4UKQCX4TYwpu+V8CMz3xlCev68d0aaKvrY jbZ+bRcIiARv3g7IhBq2D2s97Zb/u+sMZ+krY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=eD3YJscYhVTGZeYsWk7WtJsvt2DVVsRSD/cXsJZc72k=; b=eB4AqZO8kOhy8dYAb+U6icit38t+v3ipY8pkePnRMq0hqX0ON62w5A0kIfJsYfJI2o NtPSmWSToUP794hN8pRB7iusdKRq5E3fhkkyCcgp/E6oEC6MBIroJCJs586sb1mg1zaN 2/+8xNVVpO18o6BKJTvhtWcwaxUccss5exokPQdw9bsQPheLAKI4XhSG4NLMdg7I39Oy LS3dQFQ4fAs3xLMLysT55E0I8TNTrxQVKUpQC1nGOT/UiOjrJ7AfYflYfkKdDiCYlBay fjv5T3ADmwJ3lgJbaXMzEiAQuIW4ZffkOJEoy8Ebg8IgUkMBHgn4SGB/KQsmsgL5EdaM sEjw== X-Gm-Message-State: AElRT7EW1g2hANv89LU6v8TFjDtLr8uTScL3hDbzGOYYXE2cZ4sb8IRJ u87p6iHEFvwEZNS5U+Nblo5Ve4Gl6sAPSdhcIoINEKEb50A= X-Google-Smtp-Source: AG47ELvr2+R9NjB7Noo1YWLAROL7PgkUPZGZyVXJ3hlGlIfNklvRRsYNElr8O8lHDmfwG0GOyM1qCshWrROKMRQuPCQ= X-Received: by 10.107.41.16 with SMTP id p16mr10609308iop.173.1521147629578; Thu, 15 Mar 2018 14:00:29 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.138.209 with HTTP; Thu, 15 Mar 2018 14:00:28 -0700 (PDT) In-Reply-To: <20180315190522.ivft6htebkmxcxnu@bivouac.eciton.net> References: <20180308152141.1028-1-ard.biesheuvel@linaro.org> <20180315190522.ivft6htebkmxcxnu@bivouac.eciton.net> From: Ard Biesheuvel Date: Thu, 15 Mar 2018 21:00:28 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacer; add cache topology information to device tree X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Mar 2018 20:54:06 -0000 Content-Type: text/plain; charset="UTF-8" On 15 March 2018 at 19:05, Leif Lindholm wrote: > On Thu, Mar 08, 2018 at 03:21:41PM +0000, Ard Biesheuvel wrote: >> Add a DT description of the size and geometry of the various levels >> of caches that are present in the SynQuacer SoC. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel > > Reviewed-by: Leif Lindholm > Pushed as ca11ac71980cdb4c1bd3b4c2c6549b90fc47b4cc Thanks >> --- >> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 4 +- >> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi | 80 ++++++++++++++++++++ >> 2 files changed, 83 insertions(+), 1 deletion(-) >> >> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> index 2db7de3d5b96..2bea91f7f2c0 100644 >> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> @@ -1,5 +1,5 @@ >> /** @file >> - * Copyright (c) 2017, Linaro Limited. All rights reserved. >> + * Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. >> * >> * This program and the accompanying materials are licensed and made >> * available under the terms and conditions of the BSD License which >> @@ -575,3 +575,5 @@ >> #size-cells = <0>; >> }; >> }; >> + >> +#include "SynQuacerCaches.dtsi" >> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi >> new file mode 100644 >> index 000000000000..1fbcd4aabfb6 >> --- /dev/null >> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi >> @@ -0,0 +1,80 @@ >> +/** @file >> + * Copyright (c) 2018, Linaro Limited. All rights reserved. >> + * >> + * This program and the accompanying materials are licensed and made >> + * available under the terms and conditions of the BSD License which >> + * accompanies this distribution. The full text of the license may be >> + * found at http://opensource.org/licenses/bsd-license.php >> + * >> + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR >> + * IMPLIED. >> + */ >> + >> +#define __L1(cpuref, l2ref) \ >> +cpuref { \ >> + i-cache-size = <0x8000>; \ >> + i-cache-line-size = <64>; \ >> + i-cache-sets = <256>; \ >> + d-cache-size = <0x8000>; \ >> + d-cache-line-size = <64>; \ >> + d-cache-sets = <128>; \ >> + l2-cache = ; \ >> +}; >> + >> +#define __L2(idx) \ >> +L2_##idx: l2-cache##idx { \ >> + cache-size = <0x40000>; \ >> + cache-line-size = <64>; \ >> + cache-sets = <256>; \ >> + cache-unified; \ >> + next-level-cache = <&L3>; \ >> +}; >> + >> +/ { >> + __L2(0) >> + __L2(1) >> + __L2(2) >> + __L2(3) >> + __L2(4) >> + __L2(5) >> + __L2(6) >> + __L2(7) >> + __L2(8) >> + __L2(9) >> + __L2(10) >> + __L2(11) >> + >> + L3: l3-cache { >> + cache-level = <3>; >> + cache-size = <0x400000>; >> + cache-line-size = <64>; >> + cache-sets = <4096>; >> + cache-unified; >> + }; >> +}; >> + >> +__L1(&CPU0, &L2_0) >> +__L1(&CPU1, &L2_0) >> +__L1(&CPU2, &L2_1) >> +__L1(&CPU3, &L2_1) >> +__L1(&CPU4, &L2_2) >> +__L1(&CPU5, &L2_2) >> +__L1(&CPU6, &L2_3) >> +__L1(&CPU7, &L2_3) >> +__L1(&CPU8, &L2_4) >> +__L1(&CPU9, &L2_4) >> +__L1(&CPU10, &L2_5) >> +__L1(&CPU11, &L2_5) >> +__L1(&CPU12, &L2_6) >> +__L1(&CPU13, &L2_6) >> +__L1(&CPU14, &L2_7) >> +__L1(&CPU15, &L2_7) >> +__L1(&CPU16, &L2_8) >> +__L1(&CPU17, &L2_8) >> +__L1(&CPU18, &L2_9) >> +__L1(&CPU19, &L2_9) >> +__L1(&CPU20, &L2_10) >> +__L1(&CPU21, &L2_10) >> +__L1(&CPU22, &L2_11) >> +__L1(&CPU23, &L2_11) >> -- >> 2.15.1 >>