From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::d41; helo=mail-io1-xd41.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd41.google.com (mail-io1-xd41.google.com [IPv6:2607:f8b0:4864:20::d41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 78296211944A7 for ; Mon, 26 Nov 2018 15:04:05 -0800 (PST) Received: by mail-io1-xd41.google.com with SMTP id a3so15406064ioc.4 for ; Mon, 26 Nov 2018 15:04:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=inVnuBhX798fWdh8bQjJPwBaeITKujb4ugYcTc2GKOA=; b=c/UKxYDOP3h/usc7TLOsYNUtUwRATt06Q20uL6qvML41Fl2xfHuCrfrPNl5n6hhQvK 75e9/2Zt9XQRmYebEaM+aLOhZ69SoUxodOuEQq4Ov0ONcKEBUyGMYLbSsv0PJyLGv8UB eftIQRCCT7r0qLlaVmcuegHTcVsTawQdS3uW4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=inVnuBhX798fWdh8bQjJPwBaeITKujb4ugYcTc2GKOA=; b=acBzCWeWhaqZFofjGGae+xZtwY1U61wPATZzD4gZnrNVP2h9/2DVebji8C2sSW4fK/ 8mur0W8Ourz5p8E+eI9NRpXUbiaVu1t/Kv75kLAL2zdlkmJDP++/J+Caw29RTPCs2on6 TmAuiELKPwERIkFg6ohjx1jW9FxTmIonF5NuY3Zsu31W4pGnFt7HlQv/kia/jPt9eR/2 aPztmk+5du0Surdjda+nyg3wBLjzR7670298/mT4hcysOSa6pKfREED44FBhfsVESV3p tx1znJDzG1rNURuP+Id+osiEEC56zO8ub+BHEAGDFOFqredRmDnw24+D0/7q/uGTEeN0 DOmQ== X-Gm-Message-State: AA+aEWYQOxN1ygoy52wp5a73QOm76trxiC4XeWy9eYMjxkQP93neQoIF Z54Pui8es/4hfCP/gJt4g/noljYvv3DpkE2B0Xp1Gg== X-Google-Smtp-Source: AFSGD/WnUFlYQr60NUt9x4D4lXbyj7HK+sqCmVyVQGs0AJddorBlIBfzoojQ6hPiXQdkCuiFVJw44SDOd0DmCnGy4O4= X-Received: by 2002:a6b:7a46:: with SMTP id k6mr23911473iop.60.1543273444242; Mon, 26 Nov 2018 15:04:04 -0800 (PST) MIME-Version: 1.0 References: <20181126223801.17121-1-ard.biesheuvel@linaro.org> <20181126223801.17121-2-ard.biesheuvel@linaro.org> In-Reply-To: From: Ard Biesheuvel Date: Tue, 27 Nov 2018 00:03:51 +0100 Message-ID: To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: "edk2-devel@lists.01.org" , Laszlo Ersek , Leif Lindholm , Auger Eric , Andrew Jones , Julien Grall Subject: Re: [PATCH v2 01/13] ArmPkg/ArmLib: add support for reading the max physical address space size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 26 Nov 2018 23:04:05 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 27 Nov 2018 at 00:02, Philippe Mathieu-Daud=C3=A9 wrote: > > On Mon, Nov 26, 2018 at 11:43 PM Philippe Mathieu-Daud=C3=A9 > wrote: > > > > On 26/11/18 23:37, Ard Biesheuvel wrote: > > > Add a helper function that returns the maximum physical address space > > > size as supported by the current CPU. > > > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > > Signed-off-by: Ard Biesheuvel > > > > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > > > > > --- > > > ArmPkg/Include/Library/ArmLib.h | 17 +++++++++++++++++ > > > ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 16 ++++++++++++++++ > > > ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 8 ++++++++ > > > 3 files changed, 41 insertions(+) > > > > > > diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library= /ArmLib.h > > > index ffda50e9d767..b22879fe6e94 100644 > > > --- a/ArmPkg/Include/Library/ArmLib.h > > > +++ b/ArmPkg/Include/Library/ArmLib.h > > > @@ -29,6 +29,17 @@ > > > #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC |= \ > > > EFI_MEMORY_WT | EFI_MEMORY_WB |= \ > > > EFI_MEMORY_UCE) > > > +// > > > +// ARM_MMU_IDMAP_RANGE defines the maximum size of the identity mapp= ing > > > +// that covers the entire address space when running in UEFI. This i= s > > > +// limited to what can architecturally be mapped using a 4 KB granul= e, > > > +// even if the hardware is capable of mapping more using larger page= s. > > > +// > > > +#ifdef MDE_CPU_ARM > > > +#define ARM_MMU_IDMAP_RANGE (1ULL << 32) > > > +#else > > > +#define ARM_MMU_IDMAP_RANGE (1ULL << 48) > > > +#endif > > > > > > /** > > > * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NO= NSECURE_* attributes. > > > @@ -733,4 +744,10 @@ ArmWriteCntvOff ( > > > UINT64 Val > > > ); > > > > > > +UINTN > > > +EFIAPI > > > +ArmGetPhysicalAddressBits ( > > > + VOID > > > + ); > > > + > > > #endif // __ARM_LIB__ > > > diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/L= ibrary/ArmLib/AArch64/ArmLibSupport.S > > > index 1ef2f61f5979..7332601241aa 100644 > > > --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > > > +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > > > @@ -196,4 +196,20 @@ ASM_FUNC(ArmWriteSctlr) > > > 3:msr sctlr_el3, x0 > > > 4:ret > > > > > > +ASM_FUNC(ArmGetPhysicalAddressBits) > > > + mrs x0, id_aa64mmfr0_el1 > > > + adr x1, .LPARanges > > > + and x0, x0, #7 > > > + ldrb w0, [x1, x0] > > > + ret > > > + > > > +// > > > +// Bits 0..2 of the AA64MFR0_EL1 system register encode the size of = the > > > +// physical address space support on this CPU: > > > +// 0 =3D=3D 32 bits, 1 =3D=3D 36 bits, etc etc > > > +// 6 and 7 are reserved > > Oops the comment is now invalid for the index =3D=3D 6. > Ah yes, I'll fix that up before adding your R-b. > > > +// > > > +.LPARanges: > > > + .byte 32, 36, 40, 42, 44, 48, 52, -1 > > > + > > > ASM_FUNCTION_REMOVE_IF_UNREFERENCED > > > diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Libra= ry/ArmLib/Arm/ArmLibSupport.S > > > index f2a517671f0a..f2f3c9a25991 100644 > > > --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > > > +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > > > @@ -165,4 +165,12 @@ ASM_FUNC(ArmWriteCpuActlr) > > > isb > > > bx lr > > > > > > +ASM_FUNC (ArmGetPhysicalAddressBits) > > > + mrc p15, 0, r0, c0, c1, 4 // MMFR0 > > > + and r0, r0, #0xf // VMSA [3:0] > > > + cmp r0, #5 // >5 implies LPAE support > > > + movlt r0, #32 // 32 bits if no LPAE > > > + movge r0, #40 // 40 bits if LPAE > > > + bx lr > > > + > > > ASM_FUNCTION_REMOVE_IF_UNREFERENCED > > >