From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=fOLsObRk; spf=pass (domain: linaro.org, ip: 209.85.221.67, mailfrom: ard.biesheuvel@linaro.org) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by groups.io with SMTP; Wed, 04 Sep 2019 05:02:13 -0700 Received: by mail-wr1-f67.google.com with SMTP id l11so12136457wrx.5 for ; Wed, 04 Sep 2019 05:02:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=zc333dpuN7M5AXPWW79LJgcFVOpfWmPyuy7cnGvV7Wc=; b=fOLsObRkzjOU7a5fV40EuJTAWKuA9HITG3fOJs2O7uNEWSFMGmtAgNlhmsznfhSmJ6 D1pebRzgqlvPNLrxd+IlcYOqyNx/YjW2LnALfyD48GNJL35qTDaLSm1WBsr5puXgYR9H Ge7ho7qdQJXX8Pvu9B+9wcx6J/xJCa4V/926/xv3Dk0cW+i2i46cSYpFWPOqv5KJlwv/ QRQasDn/0X3K5xpSdbP9WPS8C8vGxAtesc8hglobiFbdbY3UItvRS5uIGH4x3F8PEcjU a1AL2y71eSfFS48ZuIJ87gBH6ZxvEzh06w50lXKM+lOaq2KFYPtiNHdzJmqp28ZkJUHw xh8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=zc333dpuN7M5AXPWW79LJgcFVOpfWmPyuy7cnGvV7Wc=; b=X/sOWHZhPWvTYg6a5GNOVqITqoRqmXcotWtx/VKmv7a9FuOdtI9d/GlBeaELNUGr2l cF/LG/QqZwZ25z1+XoYMB/P/k4QhmoKITEErMdt6wonR8pvSARgoFblYs9wbBzChge1U 7cvyNPw28ER4ROhTRXujeXyuMaJgZEJJItKqW6cJJbXZsRw45H9fxV3jbnaN9slM2HJJ FbkP+DbFRy1bKtA8iFtaj7ZOGz0TUN+8e/nisjiWgmtZ/l7t09iqiuaL1kCVF2reUCkf gjP76ggG2ZI4o1cOn2Shh2vcpc7vx7WS0TNz2QqrPQ4bkhxdrLy/PcIAEbUv7Z6JkwmI hvgA== X-Gm-Message-State: APjAAAWy0KIggDSi5NAmyHcM/yCsrkaCi5wpBnrVMo26Y6+SFGrx0ZKF epHp4ovklREEA/mnsLTYc7mDLLyLLJsOnUIcAF4qYw== X-Google-Smtp-Source: APXvYqyIhn8whxDQblbpZs5qtGdquKil4XZ843tR1hOSIZ3tgTOrsCsMzNDxiC4BmyttVXXhX184MK6QdFf/l8qwox0= X-Received: by 2002:a05:6000:128d:: with SMTP id f13mr49289572wrx.241.1567598531450; Wed, 04 Sep 2019 05:02:11 -0700 (PDT) MIME-Version: 1.0 References: <20190904041733.12741-1-ard.biesheuvel@linaro.org> <20190904114933.GG29255@bivouac.eciton.net> In-Reply-To: <20190904114933.GG29255@bivouac.eciton.net> From: "Ard Biesheuvel" Date: Wed, 4 Sep 2019 05:01:58 -0700 Message-ID: Subject: Re: [PATCH] BaseTools/GenFw AARCH64: fix up GOT based relative relocations To: Leif Lindholm Cc: edk2-devel-groups-io , "Gao, Liming" Content-Type: text/plain; charset="UTF-8" On Wed, 4 Sep 2019 at 04:49, Leif Lindholm wrote: > > On Tue, Sep 03, 2019 at 09:17:33PM -0700, Ard Biesheuvel wrote: > > We take great care to avoid GOT based relocations in EDK2 executables, > > primarily because they are pointless - we don't care about things like > > the CoW footprint or relocations that target read-only sections, and so > > GOT entries only bloat the binary. > > > > However, in some cases (e.g., when building the relocatable PrePi SEC > > module in ArmVirtPkg with the CLANG38 toolchain), we may end up with > > some GOT based relocations nonetheless, which break the build since > > GenFw does not know how to deal with them. > > > > The relocations emitted in this case are ADRP/LDR instruction pairs > > that are annotated as GOT based, which means that it is the linker's > > job to emit the GOT entry and tag it with an appropriate dynamic > > relocation that ensures that the correct absolute value is stored into > > the GOT entry when the executable is loaded. This dynamic relocation > > not visible to GenFw, and so populating the PE/COFF relocation section > > for these entries is non-trivial. > > > > Since each ADRP/LDR pair refers to a single symbol that is local to the > > binary (given that shared libraries are not supported), we can actually > > convert the ADRP/LDR pair into an ADRP/ADD pair that produces the symbol > > address directly rather than loading it from memory. This leaves the > > GOT entry in the binary, but since it is now unused, it is no longer > > necessary to emit a PE/COFF relocation entry for it. > > > > Signed-off-by: Ard Biesheuvel > > This is a very neat fix. My only concern is that I am not able to > reproduce the issue on my local Buster with clang7 (default). Is it > reproducible with clang8? > I managed to reproduce it on Ubuntu Bionic with clang 6. It may also be related to the version of ld.gold or the LLVM gold plugin. You should be able to test this patch for correctness by stripping the no-pie/no-pic options from the GCC5 command line, and checking any produced .dll with readelf -r to see whether any GOT based relocations were emitted, and whether the resulting binary still runs. I will do the same locally. > > --- > > BaseTools/Source/C/GenFw/Elf64Convert.c | 28 +++++++++++++++++++- > > 1 file changed, 27 insertions(+), 1 deletion(-) > > > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c > > index 3d6319c821e9..d574300ac4fe 100644 > > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c > > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c > > @@ -1017,6 +1017,31 @@ WriteSections64 ( > > } else if (mEhdr->e_machine == EM_AARCH64) { > > > > switch (ELF_R_TYPE(Rel->r_info)) { > > + INT64 Offset; > > + > > + case R_AARCH64_LD64_GOT_LO12_NC: > > + // > > + // Convert into an ADD instruction - see R_AARCH64_ADR_GOT_PAGE below. > > + // > > + *(UINT32 *)Targ &= 0x3ff; > > + *(UINT32 *)Targ |= 0x91000000 | ((Sym->st_value & 0xfff) << 10); > > + break; > > + > > + case R_AARCH64_ADR_GOT_PAGE: > > + // > > + // This relocation points to the GOT entry that contains the absolute > > + // address of the symbol we are referring to. Since EDK2 only uses > > + // fully linked binaries, we can avoid the indirection, and simply > > + // refer to the symbol directly. This implies having to patch the > > + // subsequent LDR instruction (covered by a R_AARCH64_LD64_GOT_LO12_NC > > + // relocation) into an ADD instruction - this is handled above. > > + // > > + Offset = (Sym->st_value - (Rel->r_offset & ~0xfff)) >> 12; > > + > > + *(UINT32 *)Targ &= 0x9000001f; > > + *(UINT32 *)Targ |= ((Offset & 0x1ffffc) << (5 - 2)) | ((Offset & 0x3) << 29); > > + > > + /* fall through */ > > > > case R_AARCH64_ADR_PREL_PG_HI21: > > // > > @@ -1037,7 +1062,6 @@ WriteSections64 ( > > // Attempt to convert the ADRP into an ADR instruction. > > // This is only possible if the symbol is within +/- 1 MB. > > // > > - INT64 Offset; > > > > // Decode the ADRP instruction > > Offset = (INT32)((*(UINT32 *)Targ & 0xffffe0) << 8); > > @@ -1212,6 +1236,8 @@ WriteRelocations64 ( > > case R_AARCH64_LDST32_ABS_LO12_NC: > > case R_AARCH64_LDST64_ABS_LO12_NC: > > case R_AARCH64_LDST128_ABS_LO12_NC: > > + case R_AARCH64_ADR_GOT_PAGE: > > + case R_AARCH64_LD64_GOT_LO12_NC: > > // > > // No fixups are required for relative relocations, provided that > > // the relative offsets between sections have been preserved in > > -- > > 2.17.1 > >