From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: Guo Heyi <heyi.guo@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>,
"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>,
Michael D Kinney <michael.d.kinney@intel.com>,
Haojian Zhuang <haojian.zhuang@linaro.org>
Subject: Re: [PATCH edk2-platforms 00/12] Hisilicon/D0x: Switch to generic PciHostBridge
Date: Thu, 7 Jun 2018 13:11:59 +0200 [thread overview]
Message-ID: <CAKv+Gu98oL1Vr+ZQHdfy9qpDykLH5s7tZ714hZJ=ORqOOeuXWQ@mail.gmail.com> (raw)
In-Reply-To: <20180417012044.GA123329@SZX1000114654>
On 17 April 2018 at 03:20, Guo Heyi <heyi.guo@linaro.org> wrote:
> Hi Ard,
>
> I tested mm -io on D05, for root bridge 4 with CPU IO address starting from
> 0x8_abff0000, and it worked; both mm -io 0x8abff0000 and mm 0x8abff0000 provided
> the same output. It seems there is no other limit for 64bit IO address after you
> fixed the issue in EFI shell mm command.
>
OK, so I think this is fine after all, even if my uneasy feeling
hasn't gone away :-)
Could you please resend the latest rebased version of the patches?
(and include the ATU fix as well)
> On Mon, Apr 16, 2018 at 09:57:09PM +0800, Guo Heyi wrote:
>> Thanks, I will test mm command and let you know the result.
>>
>> Regards,
>>
>> Heyi
>>
>> On Fri, Apr 13, 2018 at 09:19:53AM +0200, Ard Biesheuvel wrote:
>> > On 13 April 2018 at 04:05, Guo Heyi <heyi.guo@linaro.org> wrote:
>> > > Hi Ard,
>> > >
>> > > Any comments?
>> > >
>> >
>> > Apologies for the delay. I have been travelling and am behind on email.
>> >
>> > > Anyway we can modify the code if you insist on using an intermediate CPU IO
>> > > address space.
>> > >
>> >
>> > I have not made up my mind yet, to be honest. I agree there is a
>> > certain elegance to merging both translations, but I am concerned that
>> > existing EDK2 code may deal poorly with I/O addresses that require
>> > more than 32 bits to express.
>> >
>> > Did you try the mm command in the shell for instance? As you know, I
>> > recently removed an artificial address range limit there, but I wonder
>> > if it uses 64-bit variables for I/O ports.
next prev parent reply other threads:[~2018-06-07 11:12 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-21 1:03 [PATCH edk2-platforms 00/12] Hisilicon/D0x: Switch to generic PciHostBridge Heyi Guo
2018-03-21 1:03 ` [PATCH edk2-platforms 01/12] Hisilicon: Enable WARN and INFO debug message Heyi Guo
2018-03-21 1:03 ` [PATCH edk2-platforms 02/12] Hisilicon/D05/PlatformPciLib: fix misuse of macro Heyi Guo
2018-03-21 1:03 ` [PATCH edk2-platforms 03/12] Hisilicon/Pci: move ATU configuration to PcieInitDxe Heyi Guo
2018-03-30 15:19 ` Ard Biesheuvel
2018-03-21 1:03 ` [PATCH edk2-platforms 04/12] Hisilicon/Pci: Merge PciPlatform into PcieInit Driver Heyi Guo
2018-03-21 1:03 ` [PATCH edk2-platforms 05/12] Hisilicon/Pci: Move EnlargeAtuConfig0() to PcieInitDxe Heyi Guo
2018-03-21 1:03 ` [PATCH edk2-platforms 06/12] Hisilicon/PlatformPciLib: add segment for each root bridge Heyi Guo
2018-03-21 1:03 ` [PATCH edk2-platforms 07/12] Hisilicon: add PciHostBridgeLib Heyi Guo
2018-03-30 15:28 ` Ard Biesheuvel
2018-03-21 1:03 ` [PATCH edk2-platforms 08/12] Hisilicon: add PciCpuIo2Dxe Heyi Guo
2018-03-30 15:30 ` Ard Biesheuvel
2018-03-21 1:03 ` [PATCH edk2-platforms 09/12] Hisilicon: add PciSegmentLib for Hi161x Heyi Guo
2018-03-21 1:03 ` [PATCH edk2-platforms 10/12] Hisilicon/D0x: Switch to generic PciHostBridge driver Heyi Guo
2018-03-30 15:34 ` Ard Biesheuvel
2018-03-21 1:03 ` [PATCH edk2-platforms 11/12] Hisilicon: remove platform specific PciHostBridge Heyi Guo
2018-03-30 15:37 ` Ard Biesheuvel
2018-03-21 1:03 ` [PATCH edk2-platforms 12/12] Hisilicon/PlatformPciLib: clear redundant felds in RESOURCE_APPETURE Heyi Guo
2018-03-28 1:05 ` [PATCH edk2-platforms 00/12] Hisilicon/D0x: Switch to generic PciHostBridge Guo Heyi
2018-03-28 9:43 ` Ard Biesheuvel
2018-03-29 0:20 ` Guo Heyi
2018-03-30 15:40 ` Ard Biesheuvel
2018-03-31 1:37 ` Guo Heyi
2018-04-13 2:05 ` Guo Heyi
2018-04-13 7:19 ` Ard Biesheuvel
2018-04-16 13:57 ` Guo Heyi
2018-04-17 1:20 ` Guo Heyi
2018-04-17 1:44 ` Guo Heyi
2018-05-31 1:02 ` heyi.guo
2018-06-07 11:11 ` Ard Biesheuvel [this message]
2018-06-22 12:58 ` gary guo
2018-06-22 14:08 ` Ard Biesheuvel
2018-06-24 11:22 ` Ard Biesheuvel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAKv+Gu98oL1Vr+ZQHdfy9qpDykLH5s7tZ714hZJ=ORqOOeuXWQ@mail.gmail.com' \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox