From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::241; helo=mail-it0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x241.google.com (mail-it0-x241.google.com [IPv6:2607:f8b0:4001:c0b::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 12812220EE13A for ; Tue, 12 Dec 2017 10:34:15 -0800 (PST) Received: by mail-it0-x241.google.com with SMTP id u62so798394ita.2 for ; Tue, 12 Dec 2017 10:38:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=sTw3kEmG5cWG1RXlbGRLUVvz1Jl1Uy+mfBFA+FL6MOw=; b=iVzVnQwRNVm44p+mxLTQQfQpyiqff3dSF9YRPCjjl14XfYl0VuTcAD43nnrycarnd8 5Z2hIqG+06v6/f0OJEmq2Zz9VfQ2Tq45ZXjBLw/ddUuNWQltNQCf6c3tDtYc9gm/YYIJ Nus2NTCKnWIV79j5WpOxo6IVW7FkVGHaG+KKs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=sTw3kEmG5cWG1RXlbGRLUVvz1Jl1Uy+mfBFA+FL6MOw=; b=P2Fx9LCC5zzDgeUbwHOqO6TsrXIsYg39lLnYNP6RetdmaWrVTevmD1MWOU8+TftaQh b1d4RqBoHZOlCFYDA30y4HL2juGo/fTsOS7gQzeWsvPf8PRbAf/M0aH3hM/p0J8Xh6ES HH+a7A8F2J8fHL41gI+7zOKkhRNtfmi38bFqM2sefzu6JLAXreSlVDH8k3ZDRaDYhrZh XNlVU4h2f+b0cYjRJqcFcCIctHKo+KNtiNi/ANPUzrXP9wIEA3z5WBc2/uKK8Moc7UgL Do94xHij+G2HScx5MA5YQDT0ypgkjRC3+D1w/jC01oaGsVUet1QNlPREHJxpg/FhLjuC 5CkQ== X-Gm-Message-State: AKGB3mLkuUKhSY3WASL0hTsqv4nOhGvthy3+FTcJQ6ywPAh2A4+z45Nt 9pT50f+8u1/PfQOezsQo6FGV804vdo5iM3rRTLWgvA== X-Google-Smtp-Source: ACJfBovTR7OM/JNEt1T7lR3M9is71ek1L7jYZj3IiNHLaX1C3w607ey1yXKgAL8JUieZn1TnsBV7YNp2LYKeqRojUKs= X-Received: by 10.36.78.212 with SMTP id r203mr870200ita.58.1513103934055; Tue, 12 Dec 2017 10:38:54 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.104.16 with HTTP; Tue, 12 Dec 2017 10:38:53 -0800 (PST) In-Reply-To: <20171212182058.e7axjy2vyimeavih@bivouac.eciton.net> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> <20171212182058.e7axjy2vyimeavih@bivouac.eciton.net> From: Ard Biesheuvel Date: Tue, 12 Dec 2017 18:38:53 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Daniel Thompson , Masami Hiramatsu Subject: Re: [PATCH edk2-platforms 0/8] SynQuacer updates X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Dec 2017 18:34:16 -0000 Content-Type: text/plain; charset="UTF-8" On 12 December 2017 at 18:20, Leif Lindholm wrote: > On Tue, Dec 12, 2017 at 10:37:59AM +0000, Ard Biesheuvel wrote: >> A round of updates for Socionext SynQuacer: >> >> - enable CPU idle states in the DT, so that the OS can put cores to sleep >> using PSCI (#1) >> - add the build number to PCDs that end up in user visible strings (#2) >> - fix a PCIe detection issue in the DeveloperBox x16 slot, by keeping PERST# >> asserted for at least 100 ms before link training (#3) >> - ignore PCIe RC #0 if no card is inserted on EVB (#4 - #6) >> - add the secondary UART to the DT for the OS to use (this is UART #0 on the >> LS connector on DeveloperBox) (#7) >> - explicitly retrain the downstream links on the Asmedia 1182/1184 PCIe >> switch, to enable Gen2 speeds > > For the patches I haven't commented on individually (1,4,6): > Reviewed-by: Leif Lindholm > Thanks. Pushed as 2b3b95cb9fc9..054921cef0f1 >> Ard Biesheuvel (7): >> Silicon/SynQuacer: enable CPU idle states in device tree >> Platform/Socionext/SynQuacer: expose build number as firmware version >> Silicon/SynQuacerPciHostBridgeLib: stall for 150 ms during PERST# >> Silicon/SynQuacerPciHostBridgeLib: enable RCs based on PCD setting >> Silicon/SynQuacer: disable PCI RC #0 DT node if disabled >> Silicon/SynQuacerEvalBoard: enable PCI #0 only when card is detected >> Silicon/SynQuacer/PlatformDxe: retrain PCIe switch links to Gen2 speed >> >> Masahisa KOJIMA (1): >> Silicon/Socionext/SynQuacer/DeviceTree: expose SCP serial port to the >> OS >> >> Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 16 ++- >> Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 1 + >> Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc | 6 +- >> Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 18 ++- >> Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 1 + >> Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc | 6 +- >> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 57 ++++---- >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c | 140 ++++++++++++++++++++ >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 13 +- >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 37 ++++++ >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 3 + >> Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 94 +++++++++++++ >> Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf | 42 ++++++ >> Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 19 ++- >> Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 4 + >> Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 58 +++++--- >> Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 70 +++++++--- >> Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 2 + >> Silicon/Socionext/SynQuacer/SynQuacer.dec | 5 + >> 19 files changed, 504 insertions(+), 88 deletions(-) >> create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c >> create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h >> create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c >> create mode 100644 Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf >> >> -- >> 2.11.0 >>