From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::142; helo=mail-it1-x142.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it1-x142.google.com (mail-it1-x142.google.com [IPv6:2607:f8b0:4864:20::142]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 45E13211CFBDF for ; Mon, 25 Feb 2019 23:40:47 -0800 (PST) Received: by mail-it1-x142.google.com with SMTP id l66so2680726itg.3 for ; Mon, 25 Feb 2019 23:40:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=IuUcf+kPXgYj/aDrPGlKgkYknMNKszwr/fU/k5nctBU=; b=kWP2+ccLii9eHZkkHGvb4EDBa5UBOg1rs62QnmEXGJ0HVQVFIKO4xnmH4lAKw4hVoc wBMU12n9Dz9h+51MK7XC7+PSkvWD0v2s/09WRK/jsTmw+me6X7wXyhkVwvIlys2YHCTo DmhEuUfmE2TnqJsXxVQzmFsRJLjFLJnWrr+DsePjLFwznpkcmlkm6vjJhLDy47DQT9ZG wIor13nASMmTW2S4wJMQ7JjhafJUUErShIeFHh5ebuHQJGqM61uGhkQAbqTj9hoEBGUt QPeblOOMAARu4F4sbzjM3AaIJzVFVpy/6PHWjCht23jTiyJGWOIXgCJWWaYfo3YmKq8Y 5Svg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=IuUcf+kPXgYj/aDrPGlKgkYknMNKszwr/fU/k5nctBU=; b=sGu+IVTW5vnuY1UCECJ/3BKICQMRaL2K1dmeqzjFE+eYrFn552e9kSK/gtv0WLwEu+ ODQXZs2BxV6CMg8kPs8laBAi0xKjeRsg55r2v8YoFIwYUmvHEjy1U7iYkgEu3gweCLEa YiZ1ngP0GOFYZXMGJ9mniJRnwM1WtMPQaau6aaHagoqkWOvp0kjH24gTLal66xS+9ISy 03m1BN3PblytgU3i4KUZ/Ce70HvDW6uj0xdovemuXvz49Y6iRxhsNwcJ7ZrYJk17GlAs RGkyOcGX1SxV+WNY3EafxEcjVhdB+1hC0yJYL78r7y/hWJxl6IC6if5JxM/RsODvvJpt 9dHg== X-Gm-Message-State: AHQUAubrjuXmwOE3rRng7xwSGHVZOIcIstwqY5ob5GHuiB2uTDTYEX43 NOed22mjyPeFfa75DGujebvJEO8ZdcN0P7R95uRK7g== X-Google-Smtp-Source: AHgI3IaYWX0L4T8OKEnjpZp3xD/PCe4dQqPZrMK/xDN61fcSFRW7kxdbUOTLkluI8A1cglGlmuSf8CYU8zbahT6W6M8= X-Received: by 2002:a02:568a:: with SMTP id u10mr12292379jad.130.1551166846458; Mon, 25 Feb 2019 23:40:46 -0800 (PST) MIME-Version: 1.0 References: <20190222194328.36248-1-sami.mujawar@arm.com> In-Reply-To: <20190222194328.36248-1-sami.mujawar@arm.com> From: Ard Biesheuvel Date: Tue, 26 Feb 2019 08:40:34 +0100 Message-ID: To: Sami Mujawar Cc: "edk2-devel@lists.01.org" , Leif Lindholm , Matteo Carlini , Stephanie Hughes-Fitt , Carl van Schaik , nd Subject: Re: [PATCH v1 1/1] ArmPkg: Fix writes to GICv3 GICD_IROUTER reg X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Feb 2019 07:40:47 -0000 Content-Type: text/plain; charset="UTF-8" On Fri, 22 Feb 2019 at 20:43, Sami Mujawar wrote: > > According to ARM Generic Interrupt Controller Architecture > Specification, GIC architecture version 3.0 and version 4.0, > GICD_IROUTER is a 64-bit register. > > Fixed code to use 64 bit MMIO write operations so that the > Aff3 value (bits [39:32]) is written to GICD_IROUTER. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Sami Mujawar > Reported-by: Carl van Schaik Thanks Sami Reviewed-by: Ard Biesheuvel Pushed as 1342d7679e10..1bb76029eff4 > --- > > The changes can be seen at https://github.com/samimujawar/edk2/tree/352_fix_gicv3_GICD_IROUTERn_v1 > > > ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > index 1558db31713a828f324a807583076b21dd3302d0..67c74f79654586f8b6e47795d3c7400b88172d6e 100644 > --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > @@ -1,6 +1,6 @@ > /** @file > * > -* Copyright (c) 2011-2017, ARM Limited. All rights reserved. > +* Copyright (c) 2011-2018, ARM Limited. All rights reserved. > * > * This program and the accompanying materials > * are licensed and made available under the terms and conditions of the BSD License > @@ -467,7 +467,7 @@ GicV3DxeInitialize ( > > // Route the SPIs to the primary CPU. SPIs start at the INTID 32 > for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) { > - MmioWrite32 ( > + MmioWrite64 ( > mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), > CpuTarget > ); > -- > 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' > >