[PATCH v1 1/1] ArmPkg: Fix writes to GICv3 GICD_IROUTER<n> reg

[PATCH v1 1/1] ArmPkg: Fix writes to GICv3 GICD_IROUTER<n> reg

[Sami Mujawar]

According to ARM Generic Interrupt Controller Architecture
Specification, GIC architecture version 3.0 and version 4.0,
GICD_IROUTER<n> is a 64-bit register.

Fixed code to use 64 bit MMIO write operations so that the
Aff3 value (bits [39:32]) is written to GICD_IROUTER<n>.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reported-by: Carl van Schaik <carl@cog.systems>
---

The changes can be seen at https://github.com/samimujawar/edk2/tree/352_fix_gicv3_GICD_IROUTERn_v1


 ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
index 1558db31713a828f324a807583076b21dd3302d0..67c74f79654586f8b6e47795d3c7400b88172d6e 100644
--- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2011-2017, ARM Limited. All rights reserved.
+*  Copyright (c) 2011-2018, ARM Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -467,7 +467,7 @@ GicV3DxeInitialize (
 
     // Route the SPIs to the primary CPU. SPIs start at the INTID 32
     for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
-      MmioWrite32 (
+      MmioWrite64 (
         mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),
         CpuTarget
         );
-- 
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'

Re: [PATCH v1 1/1] ArmPkg: Fix writes to GICv3 GICD_IROUTER<n> reg

[Ard Biesheuvel]

On Fri, 22 Feb 2019 at 20:43, Sami Mujawar <sami.mujawar@arm.com> wrote:
>
> According to ARM Generic Interrupt Controller Architecture
> Specification, GIC architecture version 3.0 and version 4.0,
> GICD_IROUTER<n> is a 64-bit register.
>
> Fixed code to use 64 bit MMIO write operations so that the
> Aff3 value (bits [39:32]) is written to GICD_IROUTER<n>.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
> Reported-by: Carl van Schaik <carl@cog.systems>

Thanks Sami

Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Pushed as 1342d7679e10..1bb76029eff4


> ---
>
> The changes can be seen at https://github.com/samimujawar/edk2/tree/352_fix_gicv3_GICD_IROUTERn_v1
>
>
>  ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
> index 1558db31713a828f324a807583076b21dd3302d0..67c74f79654586f8b6e47795d3c7400b88172d6e 100644
> --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
> +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
> @@ -1,6 +1,6 @@
>  /** @file
>  *
> -*  Copyright (c) 2011-2017, ARM Limited. All rights reserved.
> +*  Copyright (c) 2011-2018, ARM Limited. All rights reserved.
>  *
>  *  This program and the accompanying materials
>  *  are licensed and made available under the terms and conditions of the BSD License
> @@ -467,7 +467,7 @@ GicV3DxeInitialize (
>
>      // Route the SPIs to the primary CPU. SPIs start at the INTID 32
>      for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
> -      MmioWrite32 (
> +      MmioWrite64 (
>          mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),
>          CpuTarget
>          );
> --
> 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'
>
>