From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by mx.groups.io with SMTP id smtpd.web12.41477.1585240605691316419 for ; Thu, 26 Mar 2020 09:36:46 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=qHybARSB; spf=pass (domain: linaro.org, ip: 209.85.128.65, mailfrom: ard.biesheuvel@linaro.org) Received: by mail-wm1-f65.google.com with SMTP id d198so7211185wmd.0 for ; Thu, 26 Mar 2020 09:36:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=AJcP4tZDzeA/M0tDbp7ubQS8Q/Q89yPpcilbMQkXWfk=; b=qHybARSBf/Q7QIIlUeEhMtBifutXFyzzIJ7tEFacRWZ4SZz7vVqrWiLftRxzP6HV1j HSN+uu4vShJUimErIJ5ufghxlUpfR2fFEdhBaSOOOm69m0WAfyP4pqjr3jJRImM+N79B RVABhbZOkiFS5mCmDTkv5B31TprvV3vonoY9lKwK+S/JO+fUFhHD0O7H1zMIMqxkZ3UO LN7CNTHCqs73brnAtotNwIQGGIC31INaNHv3iK6hzbIb17JQcY+ZRlEy+WYSFb37Zam6 fyMkZFxSzkDEBKNtFgHfbtgm1wnt5+PepkhjDjML6rjSB7F4Xu8DPjVZyUUrAuxSXD0o HKkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=AJcP4tZDzeA/M0tDbp7ubQS8Q/Q89yPpcilbMQkXWfk=; b=sEJkH91iT554drIE/u5S1BLCDhKxey7/3DnqFq6yguhfA9ffdLcehOJfCMdM1ljtBI PVZHSqkFl8514N+sJ9zJVKfYYIX6Ps9Jf5eUrr3ravK3IEliAioqUAxTimqxNJ2SUObi L0wSqy+y/elY2OkIE7iOft/bYEQ8Q1WPk+qiKbaGUFKqapjpM5iGUn9UpzbiaNifmf5X FpsNAC57ii57SZ7Muldg8f/WQJeFzP7ByzmX5t124oeR4VfVDoi+dRur+cPEdCKY5tf5 sgXejdfVPCSFEUs9+CS8p8p5GVOFmrUTr5clpfLqaa//B+O6Mrd1Ngbir3OXk8Q/22OU gghw== X-Gm-Message-State: ANhLgQ346rku2JYwNNYZiwVk5c9w2EXvSSd95dk6zRFRE36vowBzfxPS heZuJF1Cqa5oRCbRgqV1xIM+SverAmMUlanGvrgUvA== X-Google-Smtp-Source: ADFU+vt4DP+0PYfEOrOPNkIbMr+hIW21PgZ5z5a8wxqCheAS8jAJiytfRWHNUBzozSvaskb3vthuVK3PBuzXoHs1LcE= X-Received: by 2002:a1c:ac8a:: with SMTP id v132mr764623wme.62.1585240604140; Thu, 26 Mar 2020 09:36:44 -0700 (PDT) MIME-Version: 1.0 References: <20200326163016.5532-1-pete@akeo.ie> In-Reply-To: <20200326163016.5532-1-pete@akeo.ie> From: "Ard Biesheuvel" Date: Thu, 26 Mar 2020 17:36:33 +0100 Message-ID: Subject: Re: [edk2-platforms][PATCH 1/1] Platform/RPi/AcpiTables: Add Static PPTT tables To: Pete Batard Cc: edk2-devel-groups-io , Leif Lindholm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Jeremy Linton Content-Type: text/plain; charset="UTF-8" On Thu, 26 Mar 2020 at 17:30, Pete Batard wrote: > > From: Jeremy Linton > > ACPI 6.2 adds a new table, which describes how processing units > are related to each other in tree like fashion. Caches are > also sprinkled throughout the tree and describe the properties > of the caches in relation to other caches and processing units. > > Add a static PPTT table with one L2 cache and an L1I/L1D cache > for each of the 4 cores. The cache size/assc/policy/etc are from > the public docs. > So the RPi3 and RPi4 have the exact same cache topology? > The source from the aslc is derived from the one in: > Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc > > Signed-off-by: Pete Batard > --- > Platform/RaspberryPi/AcpiTables/AcpiTables.h | 18 +++ > Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 1 + > Platform/RaspberryPi/AcpiTables/Pptt.aslc | 169 ++++++++++++++++++++ > 3 files changed, 188 insertions(+) > > diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.h b/Platform/RaspberryPi/AcpiTables/AcpiTables.h > index dfae763d8107..9ee202255939 100644 > --- a/Platform/RaspberryPi/AcpiTables/AcpiTables.h > +++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.h > @@ -136,6 +136,15 @@ typedef struct > #define BCM2836_MMCHS1_INTERRUPT 0x5E > #define BCM2836_MINI_UART_INTERRUPT 0x3D > #define BCM2836_PL011_UART_INTERRUPT 0x59 > +#define CORTEX_L1D_SIZE SIZE_16KB > +#define CORTEX_L1D_SETS 64 > +#define CORTEX_L1D_ASSC 4 > +#define CORTEX_L1I_SIZE SIZE_16KB > +#define CORTEX_L1I_SETS 128 > +#define CORTEX_L1I_ASSC 2 > +#define CORTEX_L2_SIZE SIZE_512KB > +#define CORTEX_L2_SETS 512 > +#define CORTEX_L2_ASSC 16 > #elif (RPI_MODEL == 4) > #define BCM2836_V3D_BUS_INTERRUPT 0x2A > #define BCM2836_DMA_INTERRUPT 0x3B > @@ -163,6 +172,15 @@ typedef struct > #define BCM2836_PL011_UART_INTERRUPT 0x99 > #define GENET_INTERRUPT0 0xBD > #define GENET_INTERRUPT1 0xBE > +#define CORTEX_L1D_SIZE SIZE_32KB > +#define CORTEX_L1D_SETS 256 > +#define CORTEX_L1D_ASSC 2 > +#define CORTEX_L1I_SIZE (3*SIZE_16KB) > +#define CORTEX_L1I_SETS 256 > +#define CORTEX_L1I_ASSC 3 > +#define CORTEX_L2_SIZE SIZE_1MB > +#define CORTEX_L2_SETS 1024 > +#define CORTEX_L2_ASSC 16 > #endif > > #endif // __ACPITABLES_H__ > diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf > index 6642541d6a0a..e6b7d791ab47 100644 > --- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf > +++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf > @@ -32,6 +32,7 @@ [Sources] > Dsdt.asl > Csrt.aslc > Spcr.aslc > + Pptt.aslc > > [Packages] > ArmPkg/ArmPkg.dec > diff --git a/Platform/RaspberryPi/AcpiTables/Pptt.aslc b/Platform/RaspberryPi/AcpiTables/Pptt.aslc > new file mode 100644 > index 000000000000..bc09e5fdaee4 > --- /dev/null > +++ b/Platform/RaspberryPi/AcpiTables/Pptt.aslc > @@ -0,0 +1,169 @@ > +/** @file > + * > + * Processor Properties Topology Table (PPTT) > + * > + * Copyright (c) 2018, Linaro Ltd. All rights reserved.
> + * > + * SPDX-License-Identifier: BSD-2-Clause-Patent > + * > + **/ > + > +#include > + > +#include "AcpiTables.h" > + > +#define NUM_CORES 4 > +#define NUM_CLUSTERS 1 > + > +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) > + > +#pragma pack(1) > +typedef struct { > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core; > + UINT32 Offset[2]; > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache; > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache; > +} ACPI_6_3_PPTT_CORE; > + > +typedef struct { > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster; > + UINT32 Offset[1]; > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache; > + ACPI_6_3_PPTT_CORE Cores[NUM_CORES]; > +} ACPI_6_3_PPTT_CLUSTER; > + > +typedef struct { > + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; > + ACPI_6_3_PPTT_CLUSTER Packages[NUM_CLUSTERS]; > +} ACPI_6_3_PPTT_STRUCTURE; > +#pragma pack() > + > +#define PPTT_CORE(pid, cid, id) { \ > + { \ > + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \ > + FIELD_OFFSET (ACPI_6_3_PPTT_CORE, DCache), \ > + {}, \ > + { \ > + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* Not PhysicalPackage */ \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \ > + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ \ > + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* identical ignored */ \ > + }, \ > + FIELD_OFFSET (ACPI_6_3_PPTT_STRUCTURE, \ > + Packages[pid]), /* Parent */ \ > + 256 * (cid) + (id), /* AcpiProcessorId */ \ > + 2, /* NumberOfPrivateResources */ \ > + }, { \ > + FIELD_OFFSET (ACPI_6_3_PPTT_STRUCTURE, \ > + Packages[pid].Cores[id].DCache), \ > + FIELD_OFFSET (ACPI_6_3_PPTT_STRUCTURE, \ > + Packages[pid].Cores[id].ICache), \ > + }, { \ > + EFI_ACPI_6_3_PPTT_TYPE_CACHE, \ > + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \ > + {}, \ > + { \ > + 1, /* SizePropertyValid */ \ > + 1, /* NumberOfSetsValid */ \ > + 1, /* AssociativityValid */ \ > + 1, /* AllocationTypeValid */ \ > + 1, /* CacheTypeValid */ \ > + 1, /* WritePolicyValid */ \ > + 1, /* LineSizeValid */ \ > + }, \ > + 0, /* NextLevelOfCache */ \ > + CORTEX_L1D_SIZE, /* Size */ \ > + CORTEX_L1D_SETS, /* NumberOfSets */ \ > + CORTEX_L1D_ASSC, /* Associativity */ \ > + { \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ > + }, \ > + 64 /* LineSize */ \ > + }, { \ > + EFI_ACPI_6_3_PPTT_TYPE_CACHE, \ > + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \ > + {}, \ > + { \ > + 1, /* SizePropertyValid */ \ > + 1, /* NumberOfSetsValid */ \ > + 1, /* AssociativityValid */ \ > + 1, /* AllocationTypeValid */ \ > + 1, /* CacheTypeValid */ \ > + 0, /* WritePolicyValid */ \ > + 1, /* LineSizeValid */ \ > + }, \ > + 0, /* NextLevelOfCache */ \ > + CORTEX_L1I_SIZE, /* Size */ \ > + CORTEX_L1I_SETS, /* NumberOfSets */ \ > + CORTEX_L1I_ASSC, /* Associativity */ \ > + { \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType */ \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \ > + 0, /* WritePolicy */ \ > + }, \ > + 64 /* LineSize */ \ > + } \ > +} > + > +#define PPTT_CLUSTER(pid, cid) { \ > + { \ > + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \ > + FIELD_OFFSET (ACPI_6_3_PPTT_CLUSTER, L2Cache), \ > + {}, \ > + { \ > + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \ > + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \ > + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* not Leaf */ \ > + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* identical cores */ \ > + }, \ > + 0, /* Parent */ \ > + 0, /* AcpiProcessorId */ \ > + 1, /* NumberOfPrivateResources */ \ > + }, { \ > + FIELD_OFFSET (ACPI_6_3_PPTT_STRUCTURE, Packages[pid].L2Cache), \ > + }, { \ > + EFI_ACPI_6_3_PPTT_TYPE_CACHE, \ > + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \ > + {}, \ > + { \ > + 1, /* SizePropertyValid */ \ > + 1, /* NumberOfSetsValid */ \ > + 1, /* AssociativityValid */ \ > + 1, /* AllocationTypeValid */ \ > + 1, /* CacheTypeValid */ \ > + 1, /* WritePolicyValid */ \ > + 1, /* LineSizeValid */ \ > + }, \ > + 0, /* NextLevelOfCache */ \ > + CORTEX_L2_SIZE, /* Size */ \ > + CORTEX_L2_SETS, /* NumberOfSets */ \ > + CORTEX_L2_ASSC, /* Associativity */ \ > + { \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \ > + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ > + }, \ > + 64 /* LineSize */ \ > + }, { \ > + PPTT_CORE(pid, cid, 0), \ > + PPTT_CORE(pid, cid, 1), \ > + PPTT_CORE(pid, cid, 2), \ > + PPTT_CORE(pid, cid, 3), \ > + } \ > +} > + > +ACPI_6_3_PPTT_STRUCTURE Pptt = { > + { > + ACPI_HEADER(EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, > + ACPI_6_3_PPTT_STRUCTURE, > + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION), > + }, { > + PPTT_CLUSTER (0, 0), > + } > +}; > + > +VOID * CONST ReferenceAcpiTable = &Pptt; > -- > 2.21.0.windows.1 >