From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::241; helo=mail-io0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x241.google.com (mail-io0-x241.google.com [IPv6:2607:f8b0:4001:c06::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8E372223230C3 for ; Fri, 16 Feb 2018 10:35:42 -0800 (PST) Received: by mail-io0-x241.google.com with SMTP id e7so5101186ioj.1 for ; Fri, 16 Feb 2018 10:41:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=sYwY1FZhDsRzVD2LSZxnoHS4B04Dq/7w67tuX5VbMdc=; b=bCtcdvo72UBnEDopLjj+6qe//abYCQEqLCT8J1SQZzhcEmd5QGBDDYfagYMPpfLlh4 ujZw2xAWmC/qeEzGljAi8UUioUn+pBOJdnzdpOdjbNGjKyBKb7OYzFMP60Dal3//MNVI hH7J1zmeIM0uO2088OP2sS6ToKrsZ9w/RFRCc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=sYwY1FZhDsRzVD2LSZxnoHS4B04Dq/7w67tuX5VbMdc=; b=q5y5RSWAefh5Tm1GR8xS2UUz1jY5a6k/shg399dw+ou3PPAeBNAps2pnhDXCj0HZhm BcjL3IjzUvdW/XGL0ubCRIOVuwTBjAwoMcQ04e60qCLtEefSCXrI/9iXChzoq3hY5B2d Da1tGcY/pkrCqFQsOZ9etQ71yXFCSKruaOKNt+aozystUyAJfgndpeYnq4PQnoX/D9fa cVPMvWoW00cr+PpbYENqm9/z1DvWfHgvTu8sW9wqJu7lmdYyGKFxfKmzb3HFn9GHu8Hb E9RWsafcjIO5B4j4COA4Rnx0vX3Tz3MJgYgucDhJfGC2umDVFkKkZm1K0h1qVm3DU039 BISQ== X-Gm-Message-State: APf1xPD8aW4Zhp0kflX0JdtXvNPwSMlRXAXKpjxR1GLFuUOsIFYrfQiS PBmLUdcLeu/IfQBFpHCqRrg7vyMsp1nSYrzvSJ5kig== X-Google-Smtp-Source: AH8x225f2/bsIn296HJ6xNRJ8CUM2Wfge/RgXJXGinKQoPtGXLiv50Ak4IgLmX1Yf1vshQyiJSRbdL6GUHLNFB/9oWE= X-Received: by 10.107.52.73 with SMTP id b70mr9831181ioa.60.1518806496455; Fri, 16 Feb 2018 10:41:36 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.138.209 with HTTP; Fri, 16 Feb 2018 10:41:36 -0800 (PST) In-Reply-To: <20180216173555.s5wwntwmwc34ioxv@bivouac.eciton.net> References: <20180215172054.27452-1-ard.biesheuvel@linaro.org> <20180216173555.s5wwntwmwc34ioxv@bivouac.eciton.net> From: Ard Biesheuvel Date: Fri, 16 Feb 2018 18:41:36 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Joakim Bech Subject: Re: [PATCH edk2-platforms 0/5] Add Secure96 mezzanine support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Feb 2018 18:35:44 -0000 Content-Type: text/plain; charset="UTF-8" On 16 February 2018 at 17:35, Leif Lindholm wrote: > On Thu, Feb 15, 2018 at 05:20:49PM +0000, Ard Biesheuvel wrote: >> This series adds preliminary support for the Secure96 mezzanine board, >> an expansion board that can be plugged into the low speed connector on >> the Socionext SynQuacer based Developer Box platform. >> >> I have attempted to implement this in a reusable way, i.e., the secure96 >> specific parts are in separate drivers which could theoretically be >> imported by other platforms as well. >> >> I am presenting this to discuss the approach. My end goal is to wire up >> the Atmel SHA204A on this board in UEFI so it can be used as a random >> number generator, but this should be mostly orthogonal (and if it isn't, >> we can add it on top). > > So, ideally I would like to see a lot more reusable code for handling > overlays, but as this is the first mezzanine board to be added I'm > actually pretty happy for it to go in[1]. > Thanks. > We may want a whiteboard session at Linaro Connect to discuss the > generic problem. > Excellent idea. > / > Leif > > [1] Apart from any potential modifications to 1-2/5. > Oh, and there's a typo in SynQuacer in the subject of 1-2/5. > >> Ard Biesheuvel (5): >> Silicon/SynQuaver/DeviceTree: add node for SPI controller >> Silicon/SynQuaver/DeviceTree: add node for I2C controller >> Platform: add support for 96boards Secure96 mezzanine adapter >> Silicon/SynQuacer/PlatformDxe: add menu option to select mezzanine >> Platform/Socionext/DeveloperBox: add Secure96 support >> >> Platform/96boards/Secure96/DeviceTree/DeviceTree.inf | 40 +++++ >> Platform/96boards/Secure96/DeviceTree/Secure96.dts | 74 ++++++++++ >> Platform/96boards/Secure96/Secure96.dec | 56 +++++++ >> Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c | 153 ++++++++++++++++++++ >> Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf | 51 +++++++ >> Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 21 +++ >> Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 6 + >> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 36 +++++ >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 8 + >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 2 + >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni | 6 + >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr | 8 + >> Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h | 6 +- >> 13 files changed, 466 insertions(+), 1 deletion(-) >> create mode 100644 Platform/96boards/Secure96/DeviceTree/DeviceTree.inf >> create mode 100644 Platform/96boards/Secure96/DeviceTree/Secure96.dts >> create mode 100644 Platform/96boards/Secure96/Secure96.dec >> create mode 100644 Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c >> create mode 100644 Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf >> >> -- >> 2.11.0 >>