[PATCH edk2-platforms 0/5] Add Secure96 mezzanine support

[PATCH edk2-platforms 0/5] Add Secure96 mezzanine support

[Ard Biesheuvel]

This series adds preliminary support for the Secure96 mezzanine board,
an expansion board that can be plugged into the low speed connector on
the Socionext SynQuacer based Developer Box platform.

I have attempted to implement this in a reusable way, i.e., the secure96
specific parts are in separate drivers which could theoretically be
imported by other platforms as well.

I am presenting this to discuss the approach. My end goal is to wire up
the Atmel SHA204A on this board in UEFI so it can be used as a random
number generator, but this should be mostly orthogonal (and if it isn't,
we can add it on top).

Ard Biesheuvel (5):
  Silicon/SynQuaver/DeviceTree: add node for SPI controller
  Silicon/SynQuaver/DeviceTree: add node for I2C controller
  Platform: add support for 96boards Secure96 mezzanine adapter
  Silicon/SynQuacer/PlatformDxe: add menu option to select mezzanine
  Platform/Socionext/DeveloperBox: add Secure96 support

 Platform/96boards/Secure96/DeviceTree/DeviceTree.inf               |  40 +++++
 Platform/96boards/Secure96/DeviceTree/Secure96.dts                 |  74 ++++++++++
 Platform/96boards/Secure96/Secure96.dec                            |  56 +++++++
 Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c               | 153 ++++++++++++++++++++
 Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf             |  51 +++++++
 Platform/Socionext/DeveloperBox/DeveloperBox.dsc                   |  21 +++
 Platform/Socionext/DeveloperBox/DeveloperBox.fdf                   |   6 +
 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi              |  36 +++++
 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c      |   8 +
 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf    |   2 +
 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni |   6 +
 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr |   8 +
 Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h            |   6 +-
 13 files changed, 466 insertions(+), 1 deletion(-)
 create mode 100644 Platform/96boards/Secure96/DeviceTree/DeviceTree.inf
 create mode 100644 Platform/96boards/Secure96/DeviceTree/Secure96.dts
 create mode 100644 Platform/96boards/Secure96/Secure96.dec
 create mode 100644 Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c
 create mode 100644 Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf

-- 
2.11.0

[PATCH edk2-platforms 1/5] Silicon/SynQuaver/DeviceTree: add node for SPI controller

[Ard Biesheuvel]

Add a node for the SPI controller to the device tree so the OS may
attach to it. This is the SPI controller that is attached to the
96boards mezzanine connector on Developer Box.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
index 9085adb326ab..ba445a50f16f 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
@@ -538,4 +538,22 @@
         clock-names = "core", "iface";
         dma-coherent;
     };
+
+    clk_alw_1_8: spi_ihclk {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <125000000>;
+        clock-output-names = "iHCLK";
+    };
+
+    spi: spi@54810000 {
+        compatible = "socionext,synquacer-spi";
+        reg = <0x0 0x54810000 0x0 0x1000>;
+        clocks = <&clk_alw_1_8>;
+        clock-names = "iHCLK";
+        socionext,use-rtm;
+        socionext,set-aces;
+        #address-cells = <1>;
+        #size-cells = <0>;
+    };
 };
-- 
2.11.0

Re: [PATCH edk2-platforms 1/5] Silicon/SynQuaver/DeviceTree: add node for SPI controller

[Leif Lindholm]

On Thu, Feb 15, 2018 at 05:20:50PM +0000, Ard Biesheuvel wrote:
> Add a node for the SPI controller to the device tree so the OS may
> attach to it. This is the SPI controller that is attached to the
> 96boards mezzanine connector on Developer Box.

Just a generic question (which also applies to the subsequent patch):
Are there any implications here with regards to this bus running in
master or slave mode?

/
    Leif

> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> index 9085adb326ab..ba445a50f16f 100644
> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> @@ -538,4 +538,22 @@
>          clock-names = "core", "iface";
>          dma-coherent;
>      };
> +
> +    clk_alw_1_8: spi_ihclk {
> +        compatible = "fixed-clock";
> +        #clock-cells = <0>;
> +        clock-frequency = <125000000>;
> +        clock-output-names = "iHCLK";
> +    };
> +
> +    spi: spi@54810000 {
> +        compatible = "socionext,synquacer-spi";
> +        reg = <0x0 0x54810000 0x0 0x1000>;
> +        clocks = <&clk_alw_1_8>;
> +        clock-names = "iHCLK";
> +        socionext,use-rtm;
> +        socionext,set-aces;
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +    };
>  };
> -- 
> 2.11.0
> 

Re: [PATCH edk2-platforms 1/5] Silicon/SynQuaver/DeviceTree: add node for SPI controller

[Ard Biesheuvel]

On 16 February 2018 at 17:00, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Thu, Feb 15, 2018 at 05:20:50PM +0000, Ard Biesheuvel wrote:
>> Add a node for the SPI controller to the device tree so the OS may
>> attach to it. This is the SPI controller that is attached to the
>> 96boards mezzanine connector on Developer Box.
>
> Just a generic question (which also applies to the subsequent patch):
> Are there any implications here with regards to this bus running in
> master or slave mode?
>

Not really, since that depends entirely on the OS. We just assert the
presence of a certain IP block at a certain memory offset, and whether
the hardware supports slave mode is left unspecified. Whether the OS
supports slave mode (for this particular IP block) is not a property
of the hardware.


>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> ---
>>  Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 18 ++++++++++++++++++
>>  1 file changed, 18 insertions(+)
>>
>> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
>> index 9085adb326ab..ba445a50f16f 100644
>> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
>> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
>> @@ -538,4 +538,22 @@
>>          clock-names = "core", "iface";
>>          dma-coherent;
>>      };
>> +
>> +    clk_alw_1_8: spi_ihclk {
>> +        compatible = "fixed-clock";
>> +        #clock-cells = <0>;
>> +        clock-frequency = <125000000>;
>> +        clock-output-names = "iHCLK";
>> +    };
>> +
>> +    spi: spi@54810000 {
>> +        compatible = "socionext,synquacer-spi";
>> +        reg = <0x0 0x54810000 0x0 0x1000>;
>> +        clocks = <&clk_alw_1_8>;
>> +        clock-names = "iHCLK";
>> +        socionext,use-rtm;
>> +        socionext,set-aces;
>> +        #address-cells = <1>;
>> +        #size-cells = <0>;
>> +    };
>>  };
>> --
>> 2.11.0
>>

Re: [PATCH edk2-platforms 1/5] Silicon/SynQuaver/DeviceTree: add node for SPI controller

[Leif Lindholm]

On Fri, Feb 16, 2018 at 06:34:30PM +0000, Ard Biesheuvel wrote:
> On 16 February 2018 at 17:00, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> > On Thu, Feb 15, 2018 at 05:20:50PM +0000, Ard Biesheuvel wrote:
> >> Add a node for the SPI controller to the device tree so the OS may
> >> attach to it. This is the SPI controller that is attached to the
> >> 96boards mezzanine connector on Developer Box.
> >
> > Just a generic question (which also applies to the subsequent patch):
> > Are there any implications here with regards to this bus running in
> > master or slave mode?
> >
> 
> Not really, since that depends entirely on the OS. We just assert the
> presence of a certain IP block at a certain memory offset, and whether
> the hardware supports slave mode is left unspecified. Whether the OS
> supports slave mode (for this particular IP block) is not a property
> of the hardware.

I was thinking more along the lines of whether the hardware supports
slave mode or not (perhaps as a synthesis option).

But, fair enough.

If you change SynQuaver -> SynQuacer in 1-2 subject lines, for the series:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> >> Contributed-under: TianoCore Contribution Agreement 1.1
> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >> ---
> >>  Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 18 ++++++++++++++++++
> >>  1 file changed, 18 insertions(+)
> >>
> >> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> >> index 9085adb326ab..ba445a50f16f 100644
> >> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> >> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> >> @@ -538,4 +538,22 @@
> >>          clock-names = "core", "iface";
> >>          dma-coherent;
> >>      };
> >> +
> >> +    clk_alw_1_8: spi_ihclk {
> >> +        compatible = "fixed-clock";
> >> +        #clock-cells = <0>;
> >> +        clock-frequency = <125000000>;
> >> +        clock-output-names = "iHCLK";
> >> +    };
> >> +
> >> +    spi: spi@54810000 {
> >> +        compatible = "socionext,synquacer-spi";
> >> +        reg = <0x0 0x54810000 0x0 0x1000>;
> >> +        clocks = <&clk_alw_1_8>;
> >> +        clock-names = "iHCLK";
> >> +        socionext,use-rtm;
> >> +        socionext,set-aces;
> >> +        #address-cells = <1>;
> >> +        #size-cells = <0>;
> >> +    };
> >>  };
> >> --
> >> 2.11.0
> >>

Re: [PATCH edk2-platforms 1/5] Silicon/SynQuaver/DeviceTree: add node for SPI controller

[Ard Biesheuvel]

On 18 February 2018 at 11:39, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Fri, Feb 16, 2018 at 06:34:30PM +0000, Ard Biesheuvel wrote:
>> On 16 February 2018 at 17:00, Leif Lindholm <leif.lindholm@linaro.org> wrote:
>> > On Thu, Feb 15, 2018 at 05:20:50PM +0000, Ard Biesheuvel wrote:
>> >> Add a node for the SPI controller to the device tree so the OS may
>> >> attach to it. This is the SPI controller that is attached to the
>> >> 96boards mezzanine connector on Developer Box.
>> >
>> > Just a generic question (which also applies to the subsequent patch):
>> > Are there any implications here with regards to this bus running in
>> > master or slave mode?
>> >
>>
>> Not really, since that depends entirely on the OS. We just assert the
>> presence of a certain IP block at a certain memory offset, and whether
>> the hardware supports slave mode is left unspecified. Whether the OS
>> supports slave mode (for this particular IP block) is not a property
>> of the hardware.
>
> I was thinking more along the lines of whether the hardware supports
> slave mode or not (perhaps as a synthesis option).
>
> But, fair enough.
>
> If you change SynQuaver -> SynQuacer in 1-2 subject lines, for the series:
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
>

Excellent, thanks. However, I am going to respin this and make it much
more generic:

- create a separate, generic MezzanineDxe driver (with its own HII menu option)
- redefine all GPIO, I2C and SPI references in terms of the 96boards
spec, e.g., GPIO-A, GPIO-B, GPIO-C

That way, you can basically specify how the LS connector has been
integrated (which I2C/SPI/GPIO), and support anything that the generic
driver supports.

This is only up to a point, of course. Using the Secure96 RNG in UEFI
requires a UEFI driver, and some I2C plumbing, but I am trying to make
that generic as well (which is feasible if the I2C bus on the LS
connector does not contain anything else that UEFI cares about)

Re: [PATCH edk2-platforms 1/5] Silicon/SynQuaver/DeviceTree: add node for SPI controller

[Leif Lindholm]

On Mon, Feb 19, 2018 at 08:20:28AM +0000, Ard Biesheuvel wrote:
> >> Not really, since that depends entirely on the OS. We just assert the
> >> presence of a certain IP block at a certain memory offset, and whether
> >> the hardware supports slave mode is left unspecified. Whether the OS
> >> supports slave mode (for this particular IP block) is not a property
> >> of the hardware.
> >
> > I was thinking more along the lines of whether the hardware supports
> > slave mode or not (perhaps as a synthesis option).
> >
> > But, fair enough.
> >
> > If you change SynQuaver -> SynQuacer in 1-2 subject lines, for the series:
> > Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> >
> 
> Excellent, thanks. However, I am going to respin this and make it much
> more generic:
> 
> - create a separate, generic MezzanineDxe driver (with its own HII menu option)
> - redefine all GPIO, I2C and SPI references in terms of the 96boards
> spec, e.g., GPIO-A, GPIO-B, GPIO-C
>
> That way, you can basically specify how the LS connector has been
> integrated (which I2C/SPI/GPIO), and support anything that the generic
> driver supports.

Excellent - that sounds exactly like what I had been hoping for
initially.

> This is only up to a point, of course. Using the Secure96 RNG in UEFI
> requires a UEFI driver, and some I2C plumbing, but I am trying to make
> that generic as well (which is feasible if the I2C bus on the LS
> connector does not contain anything else that UEFI cares about)

I would hope that's generally the case, and otherwise we'd need to
create some protocol that lets you mux?

I.e., even if we do somethign crazy like support stacking mezzanine
boards, an abstracted mezzanine driver should be able to deal with it
- the only issue would come if there were on-board devices on the same
bus?

/
    Leif

[PATCH edk2-platforms 2/5] Silicon/SynQuaver/DeviceTree: add node for I2C controller

[Ard Biesheuvel]

Add a node for the I2C controller #1 to the device tree so the OS
may attach to it. This is the I2C controller that is attached to the
96boards mezzanine connector on Developer Box.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
index ba445a50f16f..9ec752956d05 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
@@ -556,4 +556,22 @@
         #address-cells = <1>;
         #size-cells = <0>;
     };
+
+    clk_i2c: i2c_pclk {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <62500000>;
+        clock-output-names = "pclk";
+    };
+
+    i2c: i2c@51210000 {
+        compatible = "socionext,synquacer-i2c";
+        reg = <0x0 0x51210000 0x0 0x1000>;
+        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk_i2c>;
+        clock-names = "pclk";
+        clock-frequency = <400>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+    };
 };
-- 
2.11.0

[PATCH edk2-platforms 3/5] Platform: add support for 96boards Secure96 mezzanine adapter

[Ard Biesheuvel]

Add an overlay device tree describing the Secure96 mezzanine adapter,
parameterised using PCDs. This allows this image, and the accompanying
driver to be incorporated into any platform that may have such a board
connected to its 96board low speed (LS) connector.

Note that this relies on runtime support for overlays, which is part of
our FdtLib implementation. However, no overlay support is required in
the device tree compiler, since this support is fairly new (and it is
rather hard to pass phandle names via PCDs anyway). So instead, the
accompanying driver retrieves the phandle of the GPIO programmatically,
and pokes it into the overlay before applying it.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/96boards/Secure96/DeviceTree/DeviceTree.inf   |  40 +++++
 Platform/96boards/Secure96/DeviceTree/Secure96.dts     |  74 ++++++++++
 Platform/96boards/Secure96/Secure96.dec                |  56 +++++++
 Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c   | 153 ++++++++++++++++++++
 Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf |  51 +++++++
 5 files changed, 374 insertions(+)

diff --git a/Platform/96boards/Secure96/DeviceTree/DeviceTree.inf b/Platform/96boards/Secure96/DeviceTree/DeviceTree.inf
new file mode 100644
index 000000000000..4bf087551a80
--- /dev/null
+++ b/Platform/96boards/Secure96/DeviceTree/DeviceTree.inf
@@ -0,0 +1,40 @@
+## @file
+#
+#  Device tree overlay for the 96boards Secure96 Mezzanine board
+#
+#  Copyright (c) 2018, Linaro Ltd. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION    = 0x0001001A
+  BASE_NAME      = Secure96DeviceTree
+  FILE_GUID      = ae548d4c-9062-4eed-835f-f510f8fc48af # gSecure96DtbFileGuid
+  MODULE_TYPE    = USER_DEFINED
+  VERSION_STRING = 1.0
+
+[Sources]
+  Secure96.dts
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Platform/96boards/Secure96/Secure96.dec
+
+[FixedPcd]
+  gSecure96TokenSpaceGuid.PcdGpioLedPolarity
+  gSecure96TokenSpaceGuid.PcdGpioLedU1
+  gSecure96TokenSpaceGuid.PcdGpioLedU2
+  gSecure96TokenSpaceGuid.PcdGpioLedU3
+  gSecure96TokenSpaceGuid.PcdGpioLedU4
+  gSecure96TokenSpaceGuid.PcdGpioParent
+  gSecure96TokenSpaceGuid.PcdSha204I2cAddress
+  gSecure96TokenSpaceGuid.PcdEcc508I2cAddress
+  gSecure96TokenSpaceGuid.PcdSpiTpmCs
diff --git a/Platform/96boards/Secure96/DeviceTree/Secure96.dts b/Platform/96boards/Secure96/DeviceTree/Secure96.dts
new file mode 100644
index 000000000000..1506a41b98de
--- /dev/null
+++ b/Platform/96boards/Secure96/DeviceTree/Secure96.dts
@@ -0,0 +1,74 @@
+/** @file
+ * Copyright (c) 2018, Linaro Limited. All rights reserved.
+ *
+ * This program and the accompanying materials are licensed and made
+ * available under the terms and conditions of the BSD License which
+ * accompanies this distribution.  The full text of the license may be
+ * found at http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED.
+ */
+
+#define GPIO_PARENT_PLACEHOLDER_PHANDLE     0x0
+
+/dts-v1/;
+/plugin/;
+
+/ {
+    fragment@0 {
+        target-path = "I2C_PARENT_PLACEHOLDER_STRING";
+        __overlay__ {
+            atsha204a {
+                compatible = "atmel,atsha204a";
+                reg = <FixedPcdGet32 (PcdSha204I2cAddress)>;
+            };
+            atecc508a {
+                compatible = "atmel,atecc508a";
+                reg = <FixedPcdGet32 (PcdEcc508I2cAddress)>;
+            };
+        };
+    };
+
+    fragment@1 {
+        target-path = "SPI_PARENT_PLACEHOLDER_STRING";
+        __overlay__ {
+            tpm {
+                compatible = "infineon,slb9670";
+                reg = <FixedPcdGet32 (PcdSpiTpmCs)>;
+                spi-max-frequency = <22500000>;
+            };
+        };
+    };
+
+    fragment@2 {
+        target-path = "/";
+        __overlay__ {
+            gpio-leds {
+                compatible = "gpio-leds";
+
+                secure96-u1 {
+                    gpios = <GPIO_PARENT_PLACEHOLDER_PHANDLE
+                            FixedPcdGet32 (PcdGpioLedU1)
+                            FixedPcdGet32 (PcdGpioLedPolarity)>;
+                };
+                secure96-u2 {
+                    gpios = <GPIO_PARENT_PLACEHOLDER_PHANDLE
+                            FixedPcdGet32 (PcdGpioLedU2)
+                            FixedPcdGet32 (PcdGpioLedPolarity)>;
+                };
+                secure96-u3 {
+                    gpios = <GPIO_PARENT_PLACEHOLDER_PHANDLE
+                            FixedPcdGet32 (PcdGpioLedU3)
+                            FixedPcdGet32 (PcdGpioLedPolarity)>;
+                };
+                secure96-u4 {
+                    gpios = <GPIO_PARENT_PLACEHOLDER_PHANDLE
+                            FixedPcdGet32 (PcdGpioLedU4)
+                            FixedPcdGet32 (PcdGpioLedPolarity)>;
+                };
+            };
+        };
+    };
+};
diff --git a/Platform/96boards/Secure96/Secure96.dec b/Platform/96boards/Secure96/Secure96.dec
new file mode 100644
index 000000000000..e2699eb324d7
--- /dev/null
+++ b/Platform/96boards/Secure96/Secure96.dec
@@ -0,0 +1,56 @@
+## @file
+#
+#  Device tree overlay for the 96boards Secure96 Mezzanine board
+#
+#  Copyright (c) 2018, Linaro Ltd. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  DEC_SPECIFICATION              = 0x0001001A
+  PACKAGE_NAME                   = Secure96
+  PACKAGE_GUID                   = 3e7de94f-01ac-47f1-a8e6-3c4a4ce1338e
+  PACKAGE_VERSION                = 0.1
+
+[Guids]
+  # PCD scope GUID
+  gSecure96TokenSpaceGuid = { 0x76eb3f47, 0x4d9f, 0x455e, { 0x8f, 0xd9, 0xcc, 0x48, 0x03, 0x87, 0xb8, 0x3e } }
+
+  # file GUID of the Secure96 DTB overlay
+  gSecure96DtbFileGuid = { 0xae548d4c, 0x9062, 0x4eed, { 0x83, 0x5f, 0xf5, 0x10, 0xf8, 0xfc, 0x48, 0xaf } }
+
+  # GUID to be installed by the platform as a protocol if the Secure96 mezzanine is present
+  gSecure96HardwarePresent = { 0x87e1c994, 0xebd9, 0x41b7, { 0x82, 0x8a, 0x4a, 0x92, 0x87, 0x14, 0x98, 0xa7 } }
+
+[PcdsFixedAtBuild]
+  # ASCII DT path to the GPIO parent node of the Secure 96 LEDs (e.g., "/gpio@51000000")
+  gSecure96TokenSpaceGuid.PcdGpioParent|""|VOID*|0x00000001
+
+  # GPIO polarity for the Secure96 LEDs (0 == GPIO_ACTIVE_HIGH, 1 == GPIO_ACTIVE_LOW)
+  gSecure96TokenSpaceGuid.PcdGpioLedPolarity|0|UINT32|0x00000002
+
+  # GPIO pin numbers for the Secure96 LEDs
+  gSecure96TokenSpaceGuid.PcdGpioLedU1|0|UINT32|0x00000003
+  gSecure96TokenSpaceGuid.PcdGpioLedU2|0|UINT32|0x00000004
+  gSecure96TokenSpaceGuid.PcdGpioLedU3|0|UINT32|0x00000005
+  gSecure96TokenSpaceGuid.PcdGpioLedU4|0|UINT32|0x00000006
+
+  # ASCII DT path to the I2C parent node of the Secure 96 (e.g., "/i2c@51210000")
+  gSecure96TokenSpaceGuid.PcdI2cParent|""|VOID*|0x00000007
+
+  gSecure96TokenSpaceGuid.PcdSha204I2cAddress|0x60|UINT32|0x00000008
+  gSecure96TokenSpaceGuid.PcdEcc508I2cAddress|0x61|UINT32|0x00000009
+
+  # ASCII DT path to the SPI parent node of the Secure 96 (e.g., "/spi@54810000")
+  gSecure96TokenSpaceGuid.PcdSpiParent|""|VOID*|0x0000000A
+
+  # SPI CS number for the Secure96 TPM
+  gSecure96TokenSpaceGuid.PcdSpiTpmCs|0|UINT32|0x0000000B
diff --git a/Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c b/Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c
new file mode 100644
index 000000000000..46c63fdfac57
--- /dev/null
+++ b/Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c
@@ -0,0 +1,153 @@
+/** @file
+  96boards Secure96 mezzanine board DXE driver.
+
+  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include <PiDxe.h>
+#include <libfdt.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesLib.h>
+#include <Library/UefiLib.h>
+
+STATIC CONST CHAR8 mLedNodes[][46] = {
+  "/fragment@2/__overlay__/gpio-leds/secure96-u1",
+  "/fragment@2/__overlay__/gpio-leds/secure96-u2",
+  "/fragment@2/__overlay__/gpio-leds/secure96-u3",
+  "/fragment@2/__overlay__/gpio-leds/secure96-u4",
+};
+
+STATIC
+VOID
+SetOverlayFragmentTarget (
+  VOID            *Overlay,
+  CONST CHAR8     *NodeName,
+  CONST CHAR8     *Target
+  )
+{
+  INT32       Node;
+  INT32       Err;
+
+  Node = fdt_path_offset (Overlay, NodeName);
+  ASSERT (Node > 0);
+
+  Err = fdt_setprop (Overlay, Node, "target-path", Target,
+          AsciiStrLen (Target) + 1);
+  if (Err) {
+    DEBUG ((DEBUG_ERROR, "%a: fdt_setprop() failed - %a\n",
+      __FUNCTION__, fdt_strerror (Err)));
+  }
+}
+
+STATIC
+VOID
+FixupOverlay (
+  VOID        *Dtb,
+  VOID        *Overlay
+  )
+{
+  INT32       Node;
+  UINT32      GpioPhandle;
+  UINTN       Idx;
+  UINT32      *GpioProp;
+  INT32       Err;
+
+  //
+  // Set the correct GPIO phandle in the LED nodes
+  //
+  Node = fdt_path_offset (Dtb, FixedPcdGetPtr (PcdGpioParent));
+  ASSERT (Node > 0);
+
+  GpioPhandle = fdt_get_phandle (Dtb, Node);
+  if (!GpioPhandle) {
+    //
+    // Node has no phandle yet -> create one
+    //
+    GpioPhandle = 1 + fdt_get_max_phandle (Dtb);
+    ASSERT (GpioPhandle >= 1);
+
+    Err = fdt_setprop_u32 (Dtb, Node, "phandle", GpioPhandle);
+    if (Err) {
+      DEBUG ((DEBUG_ERROR,
+        "%a: fdt_setprop_u32(.., .., \"phandle\", 0x%x) failed - %a\n",
+        __FUNCTION__, GpioPhandle, fdt_strerror (Err)));
+    }
+  }
+
+  for (Idx = 0; Idx < ARRAY_SIZE (mLedNodes); Idx++) {
+    Node = fdt_path_offset (Overlay, mLedNodes[Idx]);
+    ASSERT (Node > 0);
+
+    GpioProp = fdt_getprop_w (Overlay, Node, "gpios", NULL);
+    ASSERT (GpioProp != NULL);
+
+    *GpioProp = cpu_to_fdt32 (GpioPhandle);
+  }
+
+  SetOverlayFragmentTarget (Overlay, "/fragment@0",
+    FixedPcdGetPtr (PcdI2cParent));
+
+  SetOverlayFragmentTarget (Overlay, "/fragment@1",
+    FixedPcdGetPtr (PcdSpiParent));
+}
+
+EFI_STATUS
+EFIAPI
+Secure96DxeEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS      Status;
+  VOID            *Dtb;
+  VOID            *Overlay;
+  UINTN           OverlaySize;
+  INT32           Err;
+
+  //
+  // Find the DTB in the configuration table array. If it isn't there, just
+  // bail without an error: we may be running on an ACPI platform even if
+  // this driver does not support it [yet].
+  //
+  Status = EfiGetSystemConfigurationTable (&gFdtTableGuid, &Dtb);
+  if (Status == EFI_NOT_FOUND) {
+    return EFI_SUCCESS;
+  }
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Load the raw overlay DTB image by its file GUID.
+  //
+  Status = GetSectionFromAnyFv (&gSecure96DtbFileGuid,
+             EFI_SECTION_RAW, 0, &Overlay, &OverlaySize);
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return EFI_NOT_FOUND;
+  }
+
+  //
+  // Fix up unresolved references in the overlay.
+  //
+  FixupOverlay (Dtb, Overlay);
+
+  //
+  // Merge the overlay with the DTB
+  //
+  Err = fdt_overlay_apply (Dtb, Overlay);
+  if (Err) {
+    DEBUG ((DEBUG_ERROR, "%a: fdt_overlay_apply() failed - %a\n",
+      __FUNCTION__, fdt_strerror (Err)));
+    return EFI_NOT_FOUND;
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf b/Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf
new file mode 100644
index 000000000000..9374f7992c25
--- /dev/null
+++ b/Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf
@@ -0,0 +1,51 @@
+## @file
+#
+#  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = Secure96Dxe
+  FILE_GUID                      = 31519ec4-65f1-4790-b223-aa9330dd75fd
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = Secure96DxeEntryPoint
+
+[Sources]
+  Secure96Dxe.c
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Platform/96boards/Secure96/Secure96.dec
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  DxeServicesLib
+  FdtLib
+  UefiDriverEntryPoint
+  UefiLib
+
+[Guids]
+  gFdtTableGuid
+  gSecure96DtbFileGuid
+  gSecure96HardwarePresent
+
+[FixedPcd]
+  gSecure96TokenSpaceGuid.PcdGpioParent
+  gSecure96TokenSpaceGuid.PcdI2cParent
+  gSecure96TokenSpaceGuid.PcdSpiParent
+
+[Depex]
+  gSecure96HardwarePresent
-- 
2.11.0

[PATCH edk2-platforms 4/5] Silicon/SynQuacer/PlatformDxe: add menu option to select mezzanine

[Ard Biesheuvel]

96boards mezzanines are not runtime discoverable, so it is up to the
user to tell the firmware what is connected. So add a pulldown entry
that allows a selection to be made: note that boards are only expected
to have a single LS connector, so a pulldown is appropriate here.

If Secure96 has been selected by the user, install the associated GUID
as a protocol, which the Secure96Dxe (which installs the DT overlay into
the device tree) has a depex on.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c      | 8 ++++++++
 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf    | 2 ++
 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni | 6 ++++++
 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr | 8 ++++++++
 Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h            | 6 +++++-
 5 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
index aab830dc3a5a..d57d1bbb52fa 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
+++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
@@ -327,5 +327,13 @@ PlatformDxeEntryPoint (
     ASSERT_EFI_ERROR (Status);
   }
 
+  if (mHiiSettings->InstalledMezzanineType == MEZZANINE_SECURE96) {
+    Handle = NULL;
+    Status = gBS->InstallProtocolInterface (&Handle,
+                    &gSecure96HardwarePresent,
+                    EFI_NATIVE_INTERFACE, NULL);
+    ASSERT_EFI_ERROR (Status);
+  }
+
   return EFI_SUCCESS;
 }
diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf
index 49d9deee57ea..f3f913609452 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf
@@ -34,6 +34,7 @@ [Packages]
   EmbeddedPkg/EmbeddedPkg.dec
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
+  Platform/96boards/Secure96/Secure96.dec
   Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec
   Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
   Silicon/Socionext/SynQuacer/SynQuacer.dec
@@ -59,6 +60,7 @@ [Guids]
   gEfiHiiPlatformSetupFormsetGuid
   gFdtTableGuid
   gNetsecNonDiscoverableDeviceGuid
+  gSecure96HardwarePresent
   gSynQuacerNonDiscoverableI2cMasterGuid
   gSynQuacerNonDiscoverableRuntimeI2cMasterGuid
   gSynQuacerPlatformFormSetGuid
diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni
index 2eca8bbba8c3..707540542616 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni
+++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni
@@ -33,3 +33,9 @@
 
 #string STR_EMMC_DISABLED              #language en-US "Disabled"
 #string STR_EMMC_ENABLED               #language en-US "Enabled"
+
+#string STR_MEZZANINE_SELECT_PROMPT    #language en-US "96boards mezzanine"
+#string STR_MEZZANINE_SELECT_HELP      #language en-US "The type of mezzanine board plugged into the 96boards LS connector"
+
+#string STR_MEZZANINE_NONE             #language en-US "None/Unknown"
+#string STR_MEZZANINE_SECURE96         #language en-US "Secure96"
diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr
index ea35e902b2d7..6c348aa0a29b 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr
+++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr
@@ -70,6 +70,14 @@ formset
         option text = STRING_TOKEN(STR_EMMC_ENABLED), value = EMMC_ENABLED, flags = 0;
     endoneof;
 
+    oneof varid = SynQuacerPlatformSettings.InstalledMezzanineType,
+        prompt      = STRING_TOKEN(STR_MEZZANINE_SELECT_PROMPT),
+        help        = STRING_TOKEN(STR_MEZZANINE_SELECT_HELP),
+        flags       = NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED,
+        option text = STRING_TOKEN(STR_MEZZANINE_NONE), value = MEZZANINE_NONE, flags = DEFAULT;
+        option text = STRING_TOKEN(STR_MEZZANINE_SECURE96), value = MEZZANINE_SECURE96, flags = 0;
+    endoneof;
+
     subtitle text = STRING_TOKEN(STR_NULL_STRING);
 
   endform;
diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h b/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h
index fbbcbd7d3eec..a723f78a738a 100644
--- a/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h
+++ b/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h
@@ -22,12 +22,16 @@
 #define PCIE_MAX_SPEED_UNLIMITED          0x0
 #define PCIE_MAX_SPEED_GEN1               0x1
 
+#define MEZZANINE_NONE                    0x0
+#define MEZZANINE_SECURE96                0x1
+
 typedef struct {
   UINT8         EnableEmmc;
   UINT8         PcieSlot0MaxSpeed;
   UINT8         PcieSlot1MaxSpeed;
   UINT8         PcieSlot2MaxSpeed;
-  UINT8         Reserved[4];
+  UINT8         InstalledMezzanineType;
+  UINT8         Reserved[3];
 } SYNQUACER_PLATFORM_VARSTORE_DATA;
 
 #endif
-- 
2.11.0

[PATCH edk2-platforms 5/5] Platform/Socionext/DeveloperBox: add Secure96 support

[Ard Biesheuvel]

Add the drivers and set the PCD values according to our integration
of the LS connector on Developer Box so that, when selected in the
menu, the device tree presented in the OS is augmented with nodes
describing the various peripherals that are present on the Secure96
mezzanine board.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 21 ++++++++++++++++++++
 Platform/Socionext/DeveloperBox/DeveloperBox.fdf |  6 ++++++
 2 files changed, 27 insertions(+)

diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
index 1e39c29d7910..39bee17dccc1 100644
--- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
+++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
@@ -33,6 +33,9 @@ [Defines]
 [BuildOptions]
   RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=0
 
+  # add ample padding to the DTC so we can apply 96boards mezzanine overlays
+  *_*_*_DTC_FLAGS = -p 1024
+
 [BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
   GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
 
@@ -396,6 +399,18 @@ [PcdsFixedAtBuild.common]
 !endif
   gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|$(BUILD_NUMBER)
 
+  #
+  # 96boards Secure96 mezzanine support
+  #
+  gSecure96TokenSpaceGuid.PcdGpioLedPolarity|0
+  gSecure96TokenSpaceGuid.PcdGpioLedU1|20
+  gSecure96TokenSpaceGuid.PcdGpioLedU2|19
+  gSecure96TokenSpaceGuid.PcdGpioLedU3|22
+  gSecure96TokenSpaceGuid.PcdGpioLedU4|21
+  gSecure96TokenSpaceGuid.PcdGpioParent|"/gpio@51000000"
+  gSecure96TokenSpaceGuid.PcdI2cParent|"/i2c@51210000"
+  gSecure96TokenSpaceGuid.PcdSpiParent|"/spi@54810000"
+
 [PcdsPatchableInModule]
   gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
   gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
@@ -642,6 +657,12 @@ [Components.common]
   SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf
 
   #
+  # 96board mezzanine support
+  #
+  Platform/96boards/Secure96/DeviceTree/DeviceTree.inf
+  Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf
+
+  #
   # I2C
   #
   Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf
diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf
index c2bc5aa85739..35e2e64c8c93 100644
--- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf
+++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf
@@ -237,6 +237,12 @@ [FV.FvMain]
   }
 
   #
+  # 96board mezzanine support
+  #
+  INF RuleOverride = DTB Platform/96boards/Secure96/DeviceTree/DeviceTree.inf
+  INF Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf
+
+  #
   # I2C
   #
   INF Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf
-- 
2.11.0

Re: [PATCH edk2-platforms 0/5] Add Secure96 mezzanine support

[Leif Lindholm]

On Thu, Feb 15, 2018 at 05:20:49PM +0000, Ard Biesheuvel wrote:
> This series adds preliminary support for the Secure96 mezzanine board,
> an expansion board that can be plugged into the low speed connector on
> the Socionext SynQuacer based Developer Box platform.
> 
> I have attempted to implement this in a reusable way, i.e., the secure96
> specific parts are in separate drivers which could theoretically be
> imported by other platforms as well.
> 
> I am presenting this to discuss the approach. My end goal is to wire up
> the Atmel SHA204A on this board in UEFI so it can be used as a random
> number generator, but this should be mostly orthogonal (and if it isn't,
> we can add it on top).

So, ideally I would like to see a lot more reusable code for handling
overlays, but as this is the first mezzanine board to be added I'm
actually pretty happy for it to go in[1].

We may want a whiteboard session at Linaro Connect to discuss the
generic problem.

/
    Leif

[1] Apart from any potential modifications to 1-2/5.
    Oh, and there's a typo in SynQuacer in the subject of 1-2/5.

> Ard Biesheuvel (5):
>   Silicon/SynQuaver/DeviceTree: add node for SPI controller
>   Silicon/SynQuaver/DeviceTree: add node for I2C controller
>   Platform: add support for 96boards Secure96 mezzanine adapter
>   Silicon/SynQuacer/PlatformDxe: add menu option to select mezzanine
>   Platform/Socionext/DeveloperBox: add Secure96 support
> 
>  Platform/96boards/Secure96/DeviceTree/DeviceTree.inf               |  40 +++++
>  Platform/96boards/Secure96/DeviceTree/Secure96.dts                 |  74 ++++++++++
>  Platform/96boards/Secure96/Secure96.dec                            |  56 +++++++
>  Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c               | 153 ++++++++++++++++++++
>  Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf             |  51 +++++++
>  Platform/Socionext/DeveloperBox/DeveloperBox.dsc                   |  21 +++
>  Platform/Socionext/DeveloperBox/DeveloperBox.fdf                   |   6 +
>  Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi              |  36 +++++
>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c      |   8 +
>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf    |   2 +
>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni |   6 +
>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr |   8 +
>  Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h            |   6 +-
>  13 files changed, 466 insertions(+), 1 deletion(-)
>  create mode 100644 Platform/96boards/Secure96/DeviceTree/DeviceTree.inf
>  create mode 100644 Platform/96boards/Secure96/DeviceTree/Secure96.dts
>  create mode 100644 Platform/96boards/Secure96/Secure96.dec
>  create mode 100644 Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c
>  create mode 100644 Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf
> 
> -- 
> 2.11.0
> 

Re: [PATCH edk2-platforms 0/5] Add Secure96 mezzanine support

[Ard Biesheuvel]

On 16 February 2018 at 17:35, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Thu, Feb 15, 2018 at 05:20:49PM +0000, Ard Biesheuvel wrote:
>> This series adds preliminary support for the Secure96 mezzanine board,
>> an expansion board that can be plugged into the low speed connector on
>> the Socionext SynQuacer based Developer Box platform.
>>
>> I have attempted to implement this in a reusable way, i.e., the secure96
>> specific parts are in separate drivers which could theoretically be
>> imported by other platforms as well.
>>
>> I am presenting this to discuss the approach. My end goal is to wire up
>> the Atmel SHA204A on this board in UEFI so it can be used as a random
>> number generator, but this should be mostly orthogonal (and if it isn't,
>> we can add it on top).
>
> So, ideally I would like to see a lot more reusable code for handling
> overlays, but as this is the first mezzanine board to be added I'm
> actually pretty happy for it to go in[1].
>

Thanks.

> We may want a whiteboard session at Linaro Connect to discuss the
> generic problem.
>

Excellent idea.

> /
>     Leif
>
> [1] Apart from any potential modifications to 1-2/5.
>     Oh, and there's a typo in SynQuacer in the subject of 1-2/5.
>
>> Ard Biesheuvel (5):
>>   Silicon/SynQuaver/DeviceTree: add node for SPI controller
>>   Silicon/SynQuaver/DeviceTree: add node for I2C controller
>>   Platform: add support for 96boards Secure96 mezzanine adapter
>>   Silicon/SynQuacer/PlatformDxe: add menu option to select mezzanine
>>   Platform/Socionext/DeveloperBox: add Secure96 support
>>
>>  Platform/96boards/Secure96/DeviceTree/DeviceTree.inf               |  40 +++++
>>  Platform/96boards/Secure96/DeviceTree/Secure96.dts                 |  74 ++++++++++
>>  Platform/96boards/Secure96/Secure96.dec                            |  56 +++++++
>>  Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c               | 153 ++++++++++++++++++++
>>  Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf             |  51 +++++++
>>  Platform/Socionext/DeveloperBox/DeveloperBox.dsc                   |  21 +++
>>  Platform/Socionext/DeveloperBox/DeveloperBox.fdf                   |   6 +
>>  Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi              |  36 +++++
>>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c      |   8 +
>>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf    |   2 +
>>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni |   6 +
>>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr |   8 +
>>  Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h            |   6 +-
>>  13 files changed, 466 insertions(+), 1 deletion(-)
>>  create mode 100644 Platform/96boards/Secure96/DeviceTree/DeviceTree.inf
>>  create mode 100644 Platform/96boards/Secure96/DeviceTree/Secure96.dts
>>  create mode 100644 Platform/96boards/Secure96/Secure96.dec
>>  create mode 100644 Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c
>>  create mode 100644 Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf
>>
>> --
>> 2.11.0
>>

Re: [PATCH edk2-platforms 0/5] Add Secure96 mezzanine support

[Ard Biesheuvel]

On 15 February 2018 at 17:20, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> This series adds preliminary support for the Secure96 mezzanine board,
> an expansion board that can be plugged into the low speed connector on
> the Socionext SynQuacer based Developer Box platform.
>
> I have attempted to implement this in a reusable way, i.e., the secure96
> specific parts are in separate drivers which could theoretically be
> imported by other platforms as well.
>
> I am presenting this to discuss the approach. My end goal is to wire up
> the Atmel SHA204A on this board in UEFI so it can be used as a random
> number generator, but this should be mostly orthogonal (and if it isn't,
> we can add it on top).
>
> Ard Biesheuvel (5):
>   Silicon/SynQuaver/DeviceTree: add node for SPI controller
>   Silicon/SynQuaver/DeviceTree: add node for I2C controller

I have pushed these two (with the title corrected)


>   Platform: add support for 96boards Secure96 mezzanine adapter
>   Silicon/SynQuacer/PlatformDxe: add menu option to select mezzanine
>   Platform/Socionext/DeveloperBox: add Secure96 support
>
>  Platform/96boards/Secure96/DeviceTree/DeviceTree.inf               |  40 +++++
>  Platform/96boards/Secure96/DeviceTree/Secure96.dts                 |  74 ++++++++++
>  Platform/96boards/Secure96/Secure96.dec                            |  56 +++++++
>  Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c               | 153 ++++++++++++++++++++
>  Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf             |  51 +++++++
>  Platform/Socionext/DeveloperBox/DeveloperBox.dsc                   |  21 +++
>  Platform/Socionext/DeveloperBox/DeveloperBox.fdf                   |   6 +
>  Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi              |  36 +++++
>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c      |   8 +
>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf    |   2 +
>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni |   6 +
>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr |   8 +
>  Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h            |   6 +-
>  13 files changed, 466 insertions(+), 1 deletion(-)
>  create mode 100644 Platform/96boards/Secure96/DeviceTree/DeviceTree.inf
>  create mode 100644 Platform/96boards/Secure96/DeviceTree/Secure96.dts
>  create mode 100644 Platform/96boards/Secure96/Secure96.dec
>  create mode 100644 Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c
>  create mode 100644 Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf
>
> --
> 2.11.0
>